Arun Ravindran

A reconfigurable low IF-zero IF receiver architecture for multi-standard wide area wireless networks

The proliferation of a large number of wireless standards motivates the investigation of a multi-standard wireless receiver architecture that uses the same hardware in meeting widely varying performance requirements. In this paper we develop an innovative low IF- zero IF reconfigurable architecture capable of realizing a single chip CMOS receiver for GSM, PCS 1900 and WCDMA wireless standards. System level analysis and derivation of block level specifications arc done for the multiple standards under consideration. Possible circuit implementations for the RF and analog baseband blocks are presented.

A 0.8V CMOS filter based on a novel low voltage operational transresistance amplifier

Operational transresistance amplifier (OTRA) is suited to low voltage operation since it minimizes stacking of transistors due to the use of shunt-shunt feedback topology. A second order low pass filter with independent tuning of DC gain, cutoff frequency and Q factor was designed based on the Tow-Thomas biquad, using a novel low voltage OTRA in 0.18 /spl mu/m CMOS technology. The filter operates at a supply of 0.8V, has a 3dB cutoff of 600kHz, VIP3 of 2.85V, input referred spot noise at 1 kHz of 115nV//spl radic/Hz and consumes 0.7mW power.

System analysis of a multi-standard direct conversion wireless receiver

Wireless devices with multi-mode function are gaining popularity, but existing multi-mode devices use separate chipsets, or separate receiver paths for different standards on the same chip. A multistandard receiver with a high level of hardware share between different standards is proposed. Measures to perform system analysis for the direct conversion architecture are analyzed and used in a Simulink model to extract design specifications for multi-standard receiver components.

An active-RC reconfigurable lowpass-polyphase Tow-Thomas biquad filter

A novel active-RC biquad is presented which can be reconfigured as a polyphase filter for a low IF wireless receiver architecture, and as a lowpass filter for a zero IF wireless receiver architecture. A second order lowpass-polyphase reconfigurable filter is implemented to illustrate the technique. A 1.8 V fully differential operational amplifier in 0.18 /spl mu/ CMOS technology is used as the active element.

A low voltage CMOS transresistance-based variable gain amplifier

This paper presents a CMOS realization of a low voltage transresistance amplifier (LVTA) that is capable of operation at a supply voltage as low as 1.5V in a 5V CMOS technology. The circuit employs current feedback to reduce stacking of devices between the supply rails and to lower voltage signal swings, enabling low voltage operation. A R-2R ladder based variable gain amplifier (VGA) designed using the LVTA shows good linearity and a closed loop gain independent of bandwidth. Measured results for a prototype fabricated in a 0.5/spl mu/ CMOS technology are presented that experimentally demonstrates the proposed approach.

Error correction in pipelined ADCs using arbitrary radix calibration

This paper presents an ADC architecture which enhances accuracy of pipelined conversion using digital calibration. The popular 1.5 bit/stage pipeline architecture is adapted to an arbitrary radix structure. Calibration algorithms that estimate gain errors for two comparators in each pipeline stage are developed using this architecture. A low-noise queueing technique which enables calibration to be performed in background without interrupting the ADC input sample stream is presented. A 12-stage pipeline ADC model is used to demonstrate the effectiveness of calibration algorithms. With 10% error in the interstage gain, calibration improves the accuracy from 5 to 11 bits. Effects of implementation issues such as gain parameter settling, intradie gain variation, and finite word length computation are studied.

A digitally generated exponential function for dB-linear CMOS variable gain amplifiers

The generation of an exponential function is required to attain a high dynamic control range and a dB-linear operation in AGC applications. In such applications, a DSP is usually an inherent part of the control loop. We present a simple way to synthesize the exponential function in the analog domain by using a DSP to generate the exponential curve values directly. For a 10-bit implementation, an accuracy of more than 0.05% and a dynamic range of 60 dB are obtained. An algorithm required for the generation of the exponential and a possible implementation are discussed. Simulation results of a 0.5 /spl mu/m CMOS implementation show the validity of the proposed approach.

A novel queuing architecture for background calibration of pipeline ADCs

A queuing architecture for background calibration of pipeline ADCs is presented. By controlling the ADC conversion rate this queue enables dynamic control of the calibration rate and achieves required gain estimates in fewer conversion cycles than previously reported designs. The queue can store any required number of input samples during the calibration cycle without contributing extra noise to the input signal path. The architecture also facilitates calibration of front-end sample and holds (S/Hs) in pipeline ADCs. Operation of the queue is demonstrated with existing background calibration algorithms and dynamic calibration rate control is demonstrated with the use of a 12-stage pipeline model. Existing queue designs are evaluated and compared qualitatively with the proposed architecture.