Arun Reddy Chada

An Improved Multiple Scattering Method for Via Structures With Axially Isotropic Modes in an Irregular Plate Pair

An improved multiple scattering method is developed for an irregular plate pair where via pad/antipad radius is electrically small and the spacing between any two vias is relatively large so that the axially anisotropic parallel plate modes can be neglected. The plate-pair impedance matrix, widely used as an important parameter in power integrity analysis and also a critical part for via coupling in the intrinsic and the physics-based via models, is found to be related to the addition theorems of the zero-order axially isotropic propagating modes. As the impedance matrix of an irregular plate pair can be calculated by many analytical and numerical methods, the relationship between the plate-pair impedance matrix and the addition theorems of the zero-order axially isotropic propagating modes enables the handling of both the mutual coupling among vias and the reflection from plate-pair edges. Thus, the conventional multiple scattering method, restricted to either an infinitely large or a finite circular plate pair, can be extended to irregular plates for the via structures described earlier. The assumptions of the method are discussed and several numerical examples are provided to validate the proposed improved method.

Impedance of an infinitely large parallel-plane pair and its applications in engineering modeling

In this paper, a closed-form expression for the impedance of an infinitely large parallel plane pair is presented. It is applicable to practical printed circuit board (PCB) design problems where there are multiple shorting vias around the signal vias of interest. With the presence of multiple shorting vias, reflections from the plane pair edges can be neglected since the shorting vias prevent the electromagnetic energy from leaking away from the local cavity around the signal vias. The self and transfer impedance expressions can be obtained using the expansion of cylindrical waves. The impedances calculated from both the rectangular cavity model and the infinitely large plane pair model for several design examples are compared to demonstrate the effectiveness of the infinite plane pair approximation.

Simulation challenges in designing high speed serial links

Signal speeds of high speed serial links double almost every generation and with these increasing speeds come a wide range of new modeling and simulation challenges. Modeling challenges involve making sure that models are passive, stable and causal. Frequency-domain models, such as scattering parameter models that have measurement noise or limited bandwidth or incorrectly performed interpolation or extrapolation operations, may exhibit non-causality and non-passivity in time domain. Simulating millions of bits in timedomain to measure the interface merit in terms of bit error rate (BER) is CPU and memory intensive. This challenge has given way to new simulation algorithms and methodologies. The challenge here is that no two simulation approaches result in the same answer. The difference between approaches is aggravated at high frequencies and with inclusion of effects like crosstalk and transmitter and receiver equalization. In this paper, the results from various simulation approaches are contrasted against each other and also against measurements to understand their inherent assumptions along with their impact in designing high speed SerDes.

A concise multiple scattering method for via array analysis in a circular plate pair

Parallel plate modes are excited by the magnetic frill currents in the via holes (anti-pads). These modes are expressed as cylindrical waves. Multiple scattering of these modes among vias as well as from the edge boundaries of the plate pair are rigorously considered with the addition theorem of the cylindrical waves. An admittance matrix is derived for the via ports at the top/bottom surfaces of the via holes. Good agreement has been found between numerical simulations and the algorithm presented.

PAM4 signaling considerations for high-speed serial links

The paper discusses current challenges and advantages of multi-level signaling for high-speed serial links, showing the differences and similarities in link-path analysis between binary and multi-level signaling. Comparison of two signaling methodologies is given from the general theory viewpoint, as well as on the basis of various tests regarding crosstalk, jitter, equalizations and different channel characteristics, such as material, impedance and overall manufacturing design sensitivity.

Crosstalk Impact of Periodic-Coupled Routing on Eye Opening of High-Speed Links in PCBs

Minimizing costs in printed circuit board layouts has led designers to use two signal layers between the reference planes, which introduce broadside coupling. Additionally, due to the fiber weave effect, designers route signal traces in a zig-zag fashion rather than in straight lines. This type of routing tends to be roughly periodic between the victim and the aggressor. The periodic-coupled routing creates periodic resonances in the near-end crosstalk and nulls in insertion loss (THRU) transfer functions as a consequence of Floquet modes. Due to the periodic resonances, the crosstalk is aggravated, which reduces the signal to crosstalk ratio. This study quantifies the effect of crosstalk due to periodic routing. In addition, design guidelines based on the angle of routing, length of period, and signaling speeds are formulated for designers using statistical bit error rate eye analysis.

Modeling broadside coupled traces using equivalent per unit length (Eq PUL) RLGC model

Increases in printed circuit board (PCB) cost is leading to denser routing of high speed signal traces and this, in turn, is increasing the crosstalk among the traces. The crosstalk between the broadside coupled traces in adjacent layers is becoming an important factor to account for as the signal speeds increase. The coupling between parallel broadside coupled traces can be modeled using multi-conductor transmission line theory based on telegrapher equations using equivalent per-unit-length (Eq PUL) resistance, inductance, capacitance, and conductance (RLCG) matrices. The same approach is not applicable for the traces crossing at an arbitrary angle. A fast methodology to develop Eq PUL RLGC models that captures the coupling physics of broadside coupled traces crossing at an angle based on geometrical parameters of the stackup, and the dielectric material properties is proposed based on the idea presented in [1]. In this paper, validation of these equivalent models is done by estimating the crosstalk impact on eye opening at a specified bit error rate (BER) at different signal speeds and results are compared against full wave models.

Efficient complex broadside coupled trace modeling and estimation of crosstalk impact using statistical BER analysis for high volume, high performance printed circuit board designs

Increase in the cost of printed circuit board (PCB) with the increase in layer count has led to the design of PCB stack-ups that have broadside coupled signals. Broadside coupling of signals in adjacent layers also leads to crosstalk that can be sometimes difficult to model and quantify in terms of its impact on receiver eye opening. The difficulty stems from the fact that in most boards, broadside coupling occurs between the signal traces at various angles and at multiple instances. The challenges involved in modeling include generating models for the broadside coupled section quickly without the overhead of time consuming full-wave simulations. Full wave simulations are time and memory intensive especially for coupled traces at an angle and real board designs can have hundreds of them. The simulation challenges include predicting the impact of crosstalk on bit error rate (BER) accurately. In this paper, the focus is on alleviating the modeling challenges by using fast equivalent per unit length (Eq. PUL) [1, 10] resistance, inductance, conductance, capacitance (RLGC) method for the broadside coupled traces crossing at an angle and to resolve the simulation challenge by seamlessly integrating the models into statistical simulation approach that can quantify the eye opening at various BERs that would help electrical designers to come up with set of design and routing guidelines that can save PCB cost and at the same time maintain electrical integrity.

Improved Transmitter Jitter Modeling for Accurate Bit Error Rate (BER) Eye Contours Using Transient Simulation of Short Bit Patterns

Increase in the signaling speeds has led to decrease in jitter budget available for the channel to pass the product specifications. The current serial link specifications are based on a bit-error-rate (BER) metric and hence there is a need to account for jitter statistically. Accurately capturing jitter through the channel is very important to have confidence in the product specifications. Current statistical eye approaches are based on either single pulse/step response or multiple edge responses, which do not account for transmitter (Tx) driver jitter accurately since jitter interaction between the edges is ignored. There is an inherent assumption in pulse/step response methods that there is zero correlation between independent responses created from 2n combinations for n cursor pulse response where n is number where the tail settles, hence one zero crossing does not impact an adjacent zero crossing. Transient simulation accurately accounts for Tx jitter but is time consuming and requires large memory when simulating very large bit sequences. A new methodology is proposed to generate BER contours that capture the Tx driver jitter and inter symbol interference (ISI) through the channel accurately using unique waveforms created from truth table bit combinations. It utilizes 2N short N bit patterns as waveforms with jitter correlation from current bit patterns into adjacent bit patterns to get equivalent transient simulation of a desired pseudo random bit sequence. The method accounts for the edge interactions from any current bit pattern to next successive bit pattern to account for ISI accurately. The statistical eye diagram generated with the above approach includes nonideal channel characteristics, including ISI, XTK from nearby aggressor channels, and jitter through the channel.

Improved MMSE algorithm for DFE optimization

The signal in channels with high-speed designs is attenuated by channel loss, inter-symbol interference, jitter, noise and crosstalk. The main way to recover the signal is by using equalizations, such as Feed-Forward Equalizer, Continuous Time-Linear Equalizer and Decision Feedback Equalizer (DFE). One of the important problems with high-speed design and channel simulations is developing fast optimization algorithms for each equalizer, as each additional tap increases the cost of the chip. The paper proposes a new efficient optimization of DFE for high-speed links. Mathematical formulation of the optimization is discussed. Different test results are given for comparison purposes.