Arvin Park

Dynamic base register caching: a technique for reducing address bus width

When address reference degrees of spatial and temporal higher order address lines carry streams exhibit high locality, many of the redundant information. By caching the higher order portions of address references in a set of dynamically allocated base registers, it becomes possible to transmit small register indices between the processor and memory instead of the high order address bits themselves. Trace driven simulations indicate that this technique can significantly reduce processor-to-memory address bus width without an appreciable loss in performance, fhereby increasing available processor bandwidth. Our resulfs imply that as much as 25% of the available 1/0 bandwidth of a processor is used less than 1% of the time.

Work-optimal asynchronous algorithms for shared memory parallel computers

This paper develops shared memory algorithms for asynchronous processor systems that require the same expected work as the best PRAM algorithms. These algorithms operate efficiently under general asynchronous processor behavior (where individual processor speeds are allowed to vary widely over time). This paper achieves these results by employing a methodology that uses randomization to schedule subtasks of a parallel program. The resulting algorithms allow processors to (i) have arbitrary asynchronous behavior, (ii) have fail-stop errors, (iii) join a computation at any time, and (iv) have no unique identifiers.This paper develops a performance metric for asynchronous parallel computations, called work, which is the total number of instructions (including busy-waiting instructions) performed by a collection of parallel processors during a computation. The main result is to compute any associative function of n variables with

The processor identity problem

O(n)

Address compression through base register caching

expected work, using up to

IOStone: a synthetic file system benchmark

n/\log n\log^* n

An analysis of the information content of address reference streams

asynchronous processors, an...

Reducing communication costs for sorting on mesh-connected and linearly connected parallel computers

Abstract This paper investigates the problem of assigning unique identifiers to processors that communicate through shared memory. Solutions to fundamental multiprocessor coordination problems such as the Mutual Exclusion Problem and the Choice Coordination Problem often rely on unique identifiers. We present a probabilistic protocol that solves this Processor Identiy Problem for asynchronous processors that communicate through a common shared memory. This protocol requires no central arbiter, and all processors start in exactly the same state. The use of our protocol simplifies shared memory processor design by eliminating the need to encode processor identifiers in system hardware or software structures.

An analysis of the information content of address and data reference streams

The paper presents a technique to reduce processor-to-memory address bandwidth by exploiting temporal and spatial locality in address reference streams. Higher order portions of address words are cached in base registers at both the processor and memory. This makes it possible to transmit small register indexes between processor and memory instead of the high order address bits themselves. Trace driven simulations indicate that base register caching reduces processor-to-memory address bandwidth up to 60% without appreciable loss in performance.<<ETX>>

Workload and implementation considerations for dynamic base register caching

This paper presents a portable benchmark called IOStone that measures file system performance on a string of file system requests that is representative of measured system loads. Instead of isolating a particular aspect of file system performance such as disk access speed, or channel bandwidth, IOStone measures performance of the entire file system which includes components of disk performance, CPU performance on file system tasks, and disk cache performance, IOStone provides a basis for comparing performance of different file system implementations. It can also guide system builders in matching processor performance with file system performance. Measurements made using the IOStone benchmark indicate that a good balance between processor performance and file system performance is rarely achieved. Version II of the C language version of IOStone is available through electronic mail from becker@iris.ucdavis.edu.

Modifying VM hardware to reduce address pin requirements

We analyze the information content of several address reference streams. Our results indicate that a new scheme, based on Dynamic Huffman Coding [Vitt87], can encode a typical 32 bit address in four to seven bits. Unlike previous schemes used to estimate the information content of address words [HaDa771 ~arnm77], our scheme is completely on-line and does not rely on preeomputation of address transition probabilities. Our results imply that at least 83% of address bits in the traces we studied contain redundant information. Although our coding scheme is too complex and computationally expensive to implement in practice, it provides a lower bound on the bandwidth that can be achieved by practical compression schemes. Through use of these address compression techniques, the number of bus lines and 1/0 pins required to transmit address information between processor and memory can be ptly reduced.