Arvind M. Patel

Optimal rectangular code for high density magnetic tapes

IBMs 6250 bpi 3420 series tape units require a powerful error-correcting code for the standard 9-track format. The optimal rectangular code (0RC), presented here, is designed to correct any single-track error or, given erasure pointers, any double-track error in the tape. The code achieves this by conforming to a rectangular codeword of which two orthogonal sides are check bits. The code is specially tailored from a general class of b-adjacent codes. The ORC can be implemented without a buffer for encoding and offers a simple error-correction mechanism. The code can be generalized to multiple-channel applications. Introduction Models 4, 6 and 8 of the IBM 3420 series tape units record 6250 bits per inch (bpi), one of the highest densities commercially available on standard !-inch 9 track tapes. To achieve this density, a number of stringent engineering requirements had to be met. Included was a fast and powerful error-correcting scheme. The standard !-inch 9-track tape system evolved through the extensive use of tapes over many years. The most frequently used 8-bit byte of information and a parity check bit are accommodated vertically in these 9 tracks. The ninth parity track is usually called the VRC (vertical redundancy check) track. In low density recording such as IBM 729 series tapes, this VRC and a longitudinal parity byte (LRC) at the end of a record were sufficient. As the bit density increased, another check byte called CRC (cyclic redundancy check) was added at the end of the record to provide track error correction such as in IBMs 800 bpi tape units [1]. In designing new tape products, compatibility with the existing 9-track standard data format is one of the prime considerations if tapes are to be recorded in different machines and interchanged freely. The new products, moreover, require a superior error-correction code because of increased bit densities and I or tape speeds and other similar reasons. The new coding scheme presented in this paper is designed to satisfy these requirements. Bit density along the direction of tape motion is conventionally much higher than that across the tape. The ratio has steadily increased from about 40 in 800 bpi tapes to two to three orders of magnitude in the current high density tape machines. As a result, most common errors are track erasures. The erroneous tracks are often identified by the loss of signal in the read amplifiers, and lor excessive phase shift in clock and detection circuits or other similar electronic indicators. The coding scheme of this paper is designed to correct this type of track error or erasure. The same scheme, moreover, corrects many random errors which may be spread over many tracks in a record. The codewords are in the form of a rectangle with two orthogonal sides as check bits, and they resemble the diagonal check scheme [2]. The encoding and decoding, however, are carried out in an algebraic manner and the redundancy is minimal. The erroneous bits along a track form a cluster-error that can be corrected as a unit in each rectangular codeword. Each rectangular codeword is processed on the fly, independent of whether cluster errors are from the same track or different tracks. It is well known that the error-correcting codes for symbols from GF(2 ) , the galois field of 2 elements, can be used for correction of clusters of b-adjacent binary symbols. The generalized Hamming codes [3-5], Reed-Solomon codes [6], and BCH codes [4] with symbols from GF(2 ) are some of the examples. These codes can be described in a binary check matrix as proposed by Cocke [7]. Bossen [3] shows a high-speed implementation using the binary matrix description. Other methods of implementing the GF(2 ) codes for 579 NOVEMBER 1974 MAGNETIC TAPE CODINO

Error recovery scheme for the IBM 3850 mass storage system

The IBM 3850 Mass Storage System (MSS) stores digital data on flexible magnetic tape media; however it is different in many respects from the conventional multitrack tape machines. In particular, the use of a single-element rotary read-write head imposes new demands in the areas of data encoding and error recovery. This paper presents a comprehensive scheme for error recovery for the 3850 MSS which features a new error-correction code in a serial, single-stripe data format. The recovery procedure is designed around resynchronizable sections of data which are rendered independent of each other in error modes through the use of zero-modulation encoding and self-contained error-detection pointers. These error-detection pointers and the resynchronization signals are utilized in conjunction with interleaved codewords of the error-correction code. The code is designed with a generating polynomial in which the roots are chosen from the set of elements of a 16-element subfield of the Galois field GF(28). This choice provides the necessary code structure for desired code capabilities and facilitates fast decoding of errors with an economical implementation of the decoder. The scheme provides correction capabilities for various combinations of mixed-mode short and long errors common to magnetic tape recording of digital data.

Optimum test patterns for parity networks

The logic related to the error detecting and/or correcting circuitry of digital computers often contains portions which calculate the parity of a collection of bits. A tree structure composed of Exclusive-OR gates is used to perform this calculation. Similar to any other circuitry, the operation of this parity tree is subject to malfunctions. A procedure for testing malfunctions in a parity tree is presented in this report.

Integrated interleaving - a novel ECC architecture

We introduce a coding method which creates a nested sequence of codes whose distances can be adjusted to fit the error statistics of a specified digital communication or storage channel. This construction permits the use of redundancy in a nonuniform manner as required by the actual digital error occurrences in the codewords. In storage applications the codewords are usually distinct interleaves of data sectors. Our construction creates redundancy which is shared by all the interleaves and is used in those interleaves in which the number of errors exceeds the first level code distance, hence the name integrated interleaving. Our construction is, in particular, suited for long block records, where its coding gains are largest. We evaluate the performance and provide a decoding algorithm for this coding scheme.

A multi-channel CRC register

The Cyclic Redundancy Check (CRC) is extremely efficient and well suited for error detection in transmission, retrieval or storage of variable length records of binary data. The cyclic check is capable of detecting nearly all patterns of error with almost negligible amount of redundancy. For example, a 16-digit (2 bytes) CRC character will detect all error-bursts of length 16 or less and better than 99.99 percent of all other error-bursts in binary records of any length. For average record length of 1000 bytes this amounts to less than 0.2 percent redundancy. Peterson and Browns paper is an excellent exposition on the subject of error detection with cyclic codes.

On-the-fly decoder for multiple byte errors

Multiple-error-correcting Reed-Solomon or BCH codes in GF(2 b ) can be used for correction of multiple burst errors in binary data. However, the relatively long time required for decoding multiple errors has been among the main objections to applying these schemes to high-performance computer products. In this paper, a decoding procedure is developed for on-the-fly correction of multiple symbol (byte) errors in Reed-Solomon or BCH codes. A new decoder architecture expands the concept of Chien search of error locations into computation of error values as well, and creates a synchronous procedure for complete on-the-fly error correction of multiple byte errors. Forneys expression for error values is further simplified, which results in substantial economies in hardware and decoding time. All division operations are eliminated from the computation of the error-locator equation, and only one division operation is required in the computation of error values. The special cases of fewer errors are processed automatically, using the corresponding smaller set of syndromes through a single set of hardware. The resultant decoder implementation is well suited for LSI chip design with pipelined data flow. The implementation is illustrated with an example.

Performance data for a six-sample look-ahead

This paper is a sequel to a previous papcr which described the (1,7)ML channel with five-sample look-ahcad detection algorithm. It presents a modification to the prevoins (I ,7)ML algorithm, which requires six-sample look-ahead and improves the performance in the presence of non-lincarities and other non-Gaussian noise components. The paper also pre- sents data comparing the (I ,7)ML channel to the convcntional peakdetection channel.

Computer-Aided Assignment of Manufacturing Tolerances

This paper discusses the problem of assigning manufacturing tolerances in the development of a tolerance chart. A quantitative model is constructed so as to consider both the tolerance capability of the various processes used in the manufacture of a part, as well as the most effective way to combine tolerances in order to establish an overall tolerance. The variations of this model are discussed along with the manual trial and error method. It appears that significant reductions in manufacturing costs can be achieved by applying the automation methods presented in this paper.

Placement of Variable Size Circuits on LSI Masterslices

With the advent of large scale integration (LSI and VLSI), logic circuit densities per chip have grown to hundreds and thousands. The arrangement of interconnected logic circuits of different sizes and shapes poses a difficult combinatorial placement problem. In this paper, an overview of techniques is presented for placing different size rectangular circuits with limited locations on the chip, considering the function of level sensitive scan design (LSSD) [1], as well as wirability and electrical constraints. The automatic placement program (APLACE), encompassing techniques to handle various constraints, was developed in IBMs Engineering Design System. An overview is presented of the technique for partitioning logic into clusters (supernodes) and breaking the image down into a rectangular grid (super locations) for initial placement. [2] Iterative techniques that improve the initial placement and satisfy wirability and electrical (D.C. and capacitance) constraints are outlined. The concepts of zero ground interchange to balance horizontal and vertical channel demand and zonal movement to distribute wiring are presented. APLACE was developed primarily for the layout of the 704 gate masterslice used extensively in IBMs System 3081, encompassing 750,000 circuits. It has been in extensive use in IBM since the early 1970s to design thousands of masterslice chips ranging from 320-1500 circuits for IBMs System 38, [3][4] System 4341, [5] System 8100, for the 5000 gate array microprocessor [6][7] and for many others. The automatic layout method, APLACE, reduces design cycle time considerably and requires little or no manual intervention.

Partitioning for VLSI Placement Problems

Two partition/interchange processes are described for solving VLSI placement problems. Explicit partitioning is used in both methods to decompose the initial large graph into several smaller graphs for initial placement and subsequent interchange optimization. Comparative runs were made between the two processes and against the interchange process without partitioning on problems involving a few hundred elements. The comparative results clearly establish the effectiveness of partitioning in enhancing the performance of interchange processes and constraining computation time growth. While the two methods described herein were developed for VLSI placement problems, they are applicable to quadratic assignment problems arising from numerous other settings.