Martin Aureliano Hassner

Algorithms for sliding block codes---An application of symbolic dynamics to information theory

Ideas which have origins in Shannons work in information theory have arisen independently in a mathematical discipline called symbolic dynamics. These ideas have been refined and developed in recent years to a point where they yield general algorithms for constructing practical coding schemes with engineering applications. In this work we prove an extension of a coding theorem of Marcus and trace a line of mathematics from abstract topological dynamics to concrete logic network diagrams.

Integrated interleaving - a novel ECC architecture

We introduce a coding method which creates a nested sequence of codes whose distances can be adjusted to fit the error statistics of a specified digital communication or storage channel. This construction permits the use of redundancy in a nonuniform manner as required by the actual digital error occurrences in the codewords. In storage applications the codewords are usually distinct interleaves of data sectors. Our construction creates redundancy which is shared by all the interleaves and is used in those interleaves in which the number of errors exceeds the first level code distance, hence the name integrated interleaving. Our construction is, in particular, suited for long block records, where its coding gains are largest. We evaluate the performance and provide a decoding algorithm for this coding scheme.

IrDA-VFIr (16 Mb/s): modulation code and system design

Devices for convenient information exchange over the wireless infrared channel are commonly found in many of todays mobile platforms for computing, communicating, and imaging. Most devices comply with the international standards promoted by the Infrared Data Association for data rates of up to 4 Mb/s. With the approval of a 16 Mb/s data rate option called Very Fast Infrared, IrDAs point-to-point usage model is extendable to applications requiring wireless connectivity beyond 4 Mb/s. We describe the design and the properties of a new modulation code specifically developed for VFIr, and discuss related system design aspects. After defining basic system requirements and modulation constraints imposed by the WIrC, we introduce a rate-2/3 run-length-limited code designed to meet these criteria. The Boolean expressions for encoding and decoding are given, and their implementation is discussed together with various aspects of system design such as scrambling, invalid sequence detection, and error propagation. Furthermore, it is shown that the specific composite nature of the new RLL modulation code enables simple and efficient generation of VFIr packet frames by encoding an equivalent packet frame assembled entirely in the codes input data domain.

A combined Reed-Solomon encoder and syndrome generator with small hardware complexity

In most applications of a Reed-Solomon codec (coder/decoder) data are either being transmitted or being received where either the encoder or the decoder is active, while the other is idle. The idea presented is to show how the encoder can be transformed such that its implementation can make use of existing decoder circuitry, requiring only little additional hardware dedicated to the encoder. In CMOS design examples which were studied the encoder hardware savings amounted to more than 90%. The architecture can easily be programmed for different error correction powers.<<ETX>>

Multilevel error-control codes for data storage channels

The authors present a coding architecture suitable for magnetic storage systems. In data storage devices, several types of errors may occur. This includes random errors as well as burst errors of different lengths. A class of error control codes is presented, based on a multilevel coding architecture, that can correct several types of errors. The parameters of the multilevel codes can be adjusted to match the probability of each error type. The decoding algorithms of these codes allow for fast-error recovery since they are based on decoding algorithms for simple codes. A class of multilevel codes is constructed, based on Reed-Solomon codes, whose redundancy is minimal. >

Signal space detection in colored noise

An appropriate adaption of the decision boundaries of the well-known signal space detector (SSD) yields a detector that whitens the input noise in the detector forward path. This new detector, called a whitening signal space detector (WSSD), offers higher reliability without increasing the dimensionality of the signal space. A WSSD can be designed by applying a transformation into the ordinary SSD case. We use the new concept to design a WSSD based on three-dimensional 110 equalization and demonstrate its feasibility and performance. The detector can be implemented with a small increase of hardware and offers a significant improvement in terms of bit error rate, especially at low to moderate channel densities.

On-the-fly error correction in data storage channels

A sequential key equation solver algorithm for Reed-Solomon codes is presented. This work is motivated by the need for Error Correction Coding (ECC) On-the-Fly (OTF) in high data rate storage devices. In these applications the ECC encoder/decoder circuitry is integrated into the device controller and the actual correction is performed in the sector buffer without any microprocessor intervention thus avoiding loss of performance due to error correction. The algorithm described computes both error locator and evaluator at the same time and bears strong resemblance to the algorithm first described by Berlekamp. Due to a modified computational structure, the algorithm presented lends itself to a more efficient parallel implementation than previously described. The result is a t-symbol error correcting implementation that requires 2t multipliers and 6t symbol storage units and has a latency of 4t cycles. The structure determined by the algorithm schedule is presented, Furthermore, we have identified a modular correction unit that can be duplicated and a control unit that generates the control signals for this correction unit. We present the circuits for this modular design which lends itself to an efficient VLSI implementation. >

Exponential series statistical modeling of track misregistration in magnetic storage channels

The authors apply the analytic method of exponential series expansion to empirical frequency distributions obtained from measurements of track misregistration (TMR) phenomena in magnetic storage head-disk-assembly (HDA) devices. Analytical expressions that represent the deviation of the empirical TMR frequency distributions from the Gaussian distribution are computed. The latter becomes the first term in a series of orthogonal functions with coefficients determined by the moments of the empirical distribution. This allows for adequately matching the tails of the empirical distributions where the Gaussian fit is poor and where HDA performance predictions are most interesting. The authors describe the computation of the exponential series coefficients for TMR empirical frequency distributions as well as the algebraic composition of these coefficients used to obtain models for the combined effect of several TMR phenomena. >

Low-complexity signal processing for ISI channels

We present-a low-complexity soft detection and soft decoding magnetic disk drive read channel with a modified soft-output signal space detector (S/sup 3/D) which uses 3D-110 equalization and an error/erasure decoding Reed Solomon (RS) code. The detector determines max-log reliability information for intersymbol interference (ISI) channels with stationary white and colored noise. It can be implemented with only little additional hardware compared to the ordinary signal space detector. The erasures of the RS code are determined by the soft information and by an additional inner error detecting code (EDC) which is matched to the error patterns of the S/sup 3/D. The proposed system permits an improvement of the decoding performance in practical hard disk applications.

Algebraic signal processing in truncated p-adic arithmetic for linear channels with memory

The authors consider bandlimited linear channels with finite memory formally described by a polynomial g(z) with integer coefficients in the variable z that represents the unit delay operator. A signal processing method that operates on blocks of finite precision samples of the channel output is presented. This signal processing method is a soft-decision algebraic decoder that operates in real truncated p-adic arithmetic in which computations are exact, i.e., there is no round-off error. It furthermore lends itself to an efficient digital implementation whose complexity is a linear function of the memory size.<<ETX>>