Aryesh Amar
Cirrus Logic
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Featured researches published by Aryesh Amar.
international solid-state circuits conference | 2000
Axel Thomsen; E. de Angel; Sherry Wu; Aryesh Amar; Lei Wang; Wai Lee
A CMOS DC measurement IC surpasses the noise performance of prior-art integrated systems. The instrumentation amplifier surpasses commercially-available stand-alone inamp solutions in 0.1 to 10 Hz noise performance. It is targeted for bridge transducer measurements where signal levels are typically of the order of a few mV. Low noise is crucial at these signal levels. In prior-art, integrated DC measurement systems the wideband noise of the instrumentation amplifier is sampled directly without anti-aliasing and thus noise performance is sacrificed for a simpler interface between amplifier and modulator. This article shows a block diagram of the IC consisting of a programmable gain instrumentation amplifier followed by a 4th-order /spl Delta//spl Sigma/ modulator, a programmable decimation filter, and a 3-wire serial interface. The inamp uses the multipath feedforward architecture that offers flexibility in low frequency applications because it separates the low frequency signal path from the high frequency path designed for stability. The architecture is modified to reduce the offset introduced by the second stage of the amplifier. It is also modified according to the reduced bandwidth requirements in the DC measurement application. Special attention is given the chopper stabilization.
Advanced A/D and D/A Conversion Techniques and Their Applications, 1999. Third International Conference on (Conf. Publ. No. 466) | 1999
Douglas F. Pastorello; Aryesh Amar; Qicheng Yu; B. Del Signore
Temperature, the most commonly measured physical property, is usually measured with ground based thermocouples that produce signals both above and below ground. This high accuracy, single-supply, converter introduces a synchronized substrate pumping technique which enables the measurement of below ground signals without corruption by substrate noise. Using a 4th order delta-sigma (DS) modulator, this 20 bit converter delivers an SNR of 108.67 dB and S/D of 110.19 dB, while consuming only 7.194 mW. An integrated instrumentation amplifier is used to get the signal to a level acceptable by the DS. A digital filter is used to eliminate the DS quantization noise. The whole chip is controlled via a 3 wire serial interface.
Archive | 1999
Aryesh Amar; Bruce P. Del Signore
Archive | 1997
Aryesh Amar; Jerome E. Johnston; Bruce P. Del Signore
Archive | 2001
Aryesh Amar; Philip Steiner
Archive | 2000
Axel Thomsen; Edwin de Angel; Sherry Wu; Aryesh Amar; Jerome E. Johnston
Archive | 1999
Aryesh Amar; Jerome E. Johnston; Donald Keith Coffey
Archive | 2003
Aryesh Amar; Brian David Trotter; Jason Powell Rhode
Archive | 2005
Kartik Nanda; Aryesh Amar; Rahul Singh; Jerome E. Johnston
Archive | 2004
Kartik Nanda; Giri N. K. Rangan; Aryesh Amar