Axel Thomsen

A five stage chopper stabilized instrumentation amplifier using feedforward compensation

A programmable gain chopper stabilized instrumentation amplifier is presented. It uses a fifth order amplifier architecture with simulated open loop gain of 200 dB. It is the first reported silicon implementation of an amplifier using multipath feedforward compensation. The instrumentation amplifier achieves noise density of 7 nV/sqrt(Hz) and THD of -110 dB with 14 mW from a single 5 V supply. It is implemented in 0.6 /spl mu/m CMOS and has an active area of 4 mm/sup 2/.

A 16-mW, 120-dB linear switched-capacitor delta-sigma modulator with dynamic biasing

A high resolution fourth-order ΔΣ ADC is presented. Power reduction techniques have been applied across many aspects of the design. A class-A amplifier was designed with bias currents optimized according to the expected activity in each clock phase. The modulator achieves a 122dB dynamic range over a 400Hz bandwidth, -123dB THD, and 16mW power consumption from a single 5V supply. It is implemented in a 0.6µm double polysilicon CMOS process, and has an active area of 2 mm2.

A 16 mW, 120 dB linear switched-capacitor delta-sigma modulator with dynamic biasing

A high resolution fourth-order ΔΣ ADC is presented. Power reduction techniques have been applied across many aspects of the design. A class-A amplifier was designed with bias currents optimized according to the expected activity in each clock phase. The modulator achieves a 122dB dynamic range over a 400Hz bandwidth, -123dB THD, and 16mW power consumption from a single 5V supply. It is implemented in a 0.6µm double polysilicon CMOS process, and has an active area of 2 mm2.

A DC measurement IC with 130 nV/sub pp/ noise in 10 Hz

A CMOS DC measurement IC surpasses the noise performance of prior-art integrated systems. The instrumentation amplifier surpasses commercially-available stand-alone inamp solutions in 0.1 to 10 Hz noise performance. It is targeted for bridge transducer measurements where signal levels are typically of the order of a few mV. Low noise is crucial at these signal levels. In prior-art, integrated DC measurement systems the wideband noise of the instrumentation amplifier is sampled directly without anti-aliasing and thus noise performance is sacrificed for a simpler interface between amplifier and modulator. This article shows a block diagram of the IC consisting of a programmable gain instrumentation amplifier followed by a 4th-order /spl Delta//spl Sigma/ modulator, a programmable decimation filter, and a 3-wire serial interface. The inamp uses the multipath feedforward architecture that offers flexibility in low frequency applications because it separates the low frequency signal path from the high frequency path designed for stability. The architecture is modified to reduce the offset introduced by the second stage of the amplifier. It is also modified according to the reduced bandwidth requirements in the DC measurement application. Special attention is given the chopper stabilization.

A 110-dB-THD, 18-mW DAC using sampling of the output and feedback to reduce distortion

A one-bit digital-to-analog converter architecture is presented that reduces distortion through the use of feedback. The only critical circuit in this architecture is identical to the first integrator of a /spl Delta//spl Sigma/ analog-to-digital converter. All other circuits in the system are embedded in the feedback loop, which reduces the effects of their nonidealities. Special attention was given to the distortion arising from the discrete-time to continuous-time interface. The feedback loop is a conditionally stable system using multipath feedforward compensation. A total harmonic distortion of -110 dB is achieved. The signal-to-noise ratio is 114 dB in 400 Hz, and out-of-band noise is below -50 dB using only one external component. The power consumption is 18 mW from a 5-V supply. Die area is 3.6 mm/sup 2/ in 0.6-/spl mu/m DPTM-CMOS technology.

Session 10 overview: DC-DC converters

The session on DC-DC converters is about improvements of power density, power efficiency and power dissipation in switched-capacitor, hybrid, and inductor-based DC-DC converters. The first paper addresses the power efficiency and power-density tradeoff of switched-capacitor power conversion. The next four papers present innovative ideas in inductor- and capacitor-assisted hybrid DC-DC converters. This is followed by two high-frequency inductor-based DC-DC converters. Finally, the last paper focuses on sub-nW DC-DC converter design.

Session 22 overview: Harvesting and wireless power

Innovation in energy harvesting continues to expand the capability to extract power from the environment through temperature differences, vibration, and solar radiation. New design methodologies for wireless power transfer and LED visible-light communication are moving the state of the art.

Session 5 overview: Analog techniques

Analog technology continues to defy simple categories. This session illustrates the diversity and vigor of modern analog circuitry. The common thread among the various papers is the improvement of energy efficiency for the various applications. Sensor nodes and consumer devices can achieve more battery life and smaller form factors. Entries span the range of operational amplifiers, Class-D audio, sensor front-ends, VGAs, and oscillators. New frontiers of precision, power, and performance are established.

A 110 dB THD, 18 mW DAC using output sampling and feedback to reduce distortion

A digital-to-analog converter (DAC) with -110 dB total harmonic distortion (THD) is required to generate signals for linearity tests of data acquisition channels and sensors. Low power and a minimal number of external components are important to the application. A 256 kHz noise shaped bit stream is provided with a maximum signal frequency of 100 Hz. The out-of-band quantization noise has to be attenuated to less than -50 dB. A topology that minimized the number of critical circuit blocks in the DAC is preferable to minimize the design tasks and risks.