Arzu Ergintav

Realization of a ROIC for 72x4 PV-IR detectors

Silicon Readout Integrated Circuits (ROIC) for HgCdTe Focal Plane Arrays of 1×4 and 72×4 photovoltaic detectors are represented. The analog circuit blocks are completely identical for both, while the digital control circuit is modified to take into account the larger array size. The manufacturing technology is 0.35μm, double poly-Si, three-metal CMOS process. ROIC structure includes four elements TDI functioning with a super sampling rate of 3, bidirectional scanning, dead pixel de-selection, automatic gain adjustment in response to pixel deselection besides programmable four gain setting (up to 2.58pC storage), and programmable integration time. ROIC has four outputs with a dynamic range of 2.8V (from 1.2V to 4V) for an output load of 10pF capacitive in parallel with 1MΩ resistance, and operates at a clock frequency of 5 MHz. The input referred noise is less than 1037 μV with 460 fF integration capacitor, corresponding to 2978 electrons.

Design of a low-jitter wideband frequency synthesizer for 802.11ad wireless OFDM systems using a frequency sixtupler

The rms timing jitter of a phase-locked loop (PLL) is calculated and minimized analytically from the VCO phase noise and the in-band phase noise plateau with and without digital baseband correction in an OFDM system. Subsequently, we present an integrated wideband frequency synthesizer in a 130 nm SiGe BiCMOS technology. An 8.7GHz-11.8GHz PLL using only one VCO is followed by a frequency sixtupler composed of a tripler and a doubler. The measured phase noise at 1 MHz offset from the 10 GHz PLL output frequency is below −108 dBc/Hz. For a 60 GHz OFDM system, this corresponds to an rms phase error of 1.5° and a PLL rms jitter of 70 fs after common phase error correction. The synthesizer chip occupies a chip area of 3.6 mm2 and draws 144 mA from a 3.3 V supply.

An integrated 240 GHz differential frequency sixtupler in SiGe BiCMOS technology

An integrated frequency sixtupler in SiGe BiCMOS technology is presented. It is composed of a nonlinear differential amplifier used as a frequency tripler followed by a Gilbert mixer used as a frequency doubler. The 3 dB bandwidth of the circuit is 15GHz in between 222 – 237GHz range with peak output power of −4 dBm for 0dBm input power. The suppression of the 120GHz feed through signal at the mixer output is better than 14 dB while the 5th and the 7th harmonics are suppressed by more than 18 dB. The circuit consumes 900mW from a 4.7V supply. It is preceded by a differential amplifier functioning as an active balun to generate differential signals for the tripler.

A 30.5 GHz fully integrated frequency synthesizer in SiGe BiCMOS for 61 GHz and 122 GHz radar applications

This paper presents a fully integrated millimeter-wave phase-locked loop (PLL) frequency synthesizer fabricated in 130nm BiCMOS technology. It comprises a self-buffered voltage controlled oscillator (VCO) tunable from 29.4 to 33.0 GHz, which corresponds to 11.5% tuning range. The VCO contains a programmable binary weighted varactor bank for phase noise reduction due to configurable low VCO gain. A programmable 4-bit charge pump (CP) was designed in order to compensate for VCO gain variation. It provides fast switching and shows low mismatch between UP and DN currents. The measured phase noise of the PLL is −85 dBc/Hz and −100 dBc/Hz at 150 kHz and 1MHz offset from the carrier, respectively. The circuit draws 60mA from 3.3 V supply. It is demonstrated that the presented chip can be successfully used in FMCW radar applications.

An integrated 122GHz differential frequency doubler with 37GHz bandwidth in 130 nm SiGe BiCMOS technology

This paper describes an integrated frequency multiplier, implemented as a Gilbert cell based frequency doubler in a 130 nm SiGe BiCMOS technology. The circuit demonstrates a 3 dB bandwidth of 97–134GHz with peak output power of 1 dBm for 1 dBm input power. The fundamental suppression, measured at the single-ended output, is better than 21 dBc while the frequency doubler consumes 69mW from a 3.3V supply. The doubler is preceded by a differential amplifier functioning as an active balun to generate a differential signal for the Gilbert cell.