Frank Herzel

A study of oscillator jitter due to supply and substrate noise

This paper investigates the timing jitter of single-ended and differential CMOS ring oscillators due to supply and substrate noise. We calculate the jitter resulting from supply and substrate noise, show that the concept of frequency modulation can be applied, and derive relationships that express different types of jitter in terms of the sensitivity of the oscillation frequency to the supply or substrate voltage. Using examples based on measured results, we show that thermal jitter is typically negligible compared to supply- and substrate-induced jitter in high-speed digital systems. We also discuss the dependence of the jitter of differential CMOS ring oscillators on transistor gate width, power consumption, and the number of stages.

An integrated CMOS RF synthesizer for 802.11a wireless LAN

A frequency synthesizer combining a relatively large tuning range (4.12-4.72 GHz) with a low noise sensitivity is presented. A stable fine-tuning loop is combined with an unstable coarse-tuning loop in parallel. As a result, a stable phase-locked loop (PLL) with a relatively wide tuning range and a moderate level of reference spurs is obtained. By adding a resistorless coarse-tuning loop, the tuning range was increased by a factor of four with no penalty in terms of phase noise, reference spurs, and settling speed. Also, the additional chip area and power consumption are negligible. The CMOS PLL circuit fabricated in a 0.25-/spl mu/m technology is aimed at multiband WLAN transceivers.

A fully integrated BiCMOS PLL for 60 GHz wireless applications

An integrated PLL aimed at wireless transceivers in the unlicensed band from 59GHz to 64GHz is described. The PLL was fabricated in a SiGe:C BiCMOS technology with both f/sub T//f/sub max/=200GHz. The measured PLL lock range is from 53.3GHz to 55.7GHz. It operates from a 3V supply except for a first divide-by-two stage which requires a 5V supply. Total power consumption is 895mW.

A fully integrated 60 GHz LNA in SiGe:C BiCMOS technology

This paper presents a SiGe differential low-noise amplifier (LNA) for the V-band. The measured gain at 60 GHz is 18 dB, and the input return loss is below -15 dB. The 3-dB bandwidth is from 49 GHz to 71 GHz. Measured and simulated S-parameters agree well over the whole range. The LNA draws 30 mA from a 2.2 V supply. It facilitates the design of a fully integrated WLAN receiver in the 57-64 GHz band.

An Integrated 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and 20–28 GHz Frequency Synthesizer for Software-Defined Radio Applications

We present an integrated frequency synthesizer which is able to provide in-phase/quadrature phase signal over the frequency bands 0.6-4.6 GHz, 5-7 GHz, 10-14 GHz, and in-phase signal over 20-28 GHz for software-defined radio applications. An integrated voltage-controlled oscillator (VCO) with 34% tuning range and a set of high-speed dividers are used to accomplish all the frequencies. To achieve a wide tuning range while keeping a low gain and a low phase noise, the VCO employs digitally controlled sub-bands. The measured PLL phase noise is - 108 dBc/Hz, -121 dBc/Hz, and -135 dBc/Hz at 1 MHz offset for 24 GHz, 4 GHz, and 700 MHz, respectively. Fabricated in a 0.25 μm SiGe BiCMOS process, the synthesizer occupies a chip area of 4.8 mm2. The synthesizer was optimized for reconfigurable base station applications, but can also be used for cognitive radio, radar systems, satellite communication, and high-speed digital clock generation.

Oscillator jitter due to supply and substrate noise

Oscillators used in digital systems experience substantial supply and substrate noise. This paper describes the timing jitter of oscillators in such applications, demonstrating that the contribution of device electronic noise is typically much less significant than that due to environmental noise. We utilize a frequency modulation model to predict the jitter, and study the effect of design parameters such as device dimensions and number of stages.

Phase noise in a differential CMOS voltage-controlled oscillator for RF applications

This paper presents theoretical and experimental results on phase noise of differential CMOS oscillators. A simple analytical expression is derived and verified by simulation which relates the phase noise including the device excess noise factor to circuit parameters. In agreement with the theoretical results, an experimental 1.9-GHz oscillator yielded phase noise as low as -100 dBc/Hz at 100-kHz offset at a power consumption of 12 mW. A wide tuning range of 250 MHz was obtained by using PMOSFETs as varicap with only slight degradation of the phase-noise performance due to the varicap.

An integrated CMOS PLL for low-jitter applications

This brief presents a fully integrated integer-N frequency synthesizer with a frequency-tuning range from 2.4 to 2.9 GHz and root-mean-square (rms) jitter below 2.5 ps over 350 MHz. The employed architecture using an inductance-capacitance (L-C) oscillator with two control inputs combines a wide tuning range with a low noise sensitivity. Potential applications include clock generation in microprocessors and clock recovery in fiberoptic receivers.

A 2.5-GHz eight-phase VCO in SiGe BiCMOS technology

We present a 2.5-GHz voltage-controlled oscillator (VCO) with eight equally distributed phases derived from a 10-GHz LC VCO. Stochastic and static phase errors were obtained by spectrum analyzer measurements in conjunction with an on-chip single-sideband mixer. From the measured phase noise spectrum, we predict an absolute rms jitter contribution of 130 fs in a 2-MHz bandwidth phase-locked loop. A static phase error of less than 0.7/spl deg/ was deduced from the sideband suppression. The eight-phase VCO is tunable from 2.35 to 2.85 GHz and draws 16 mA from a 2.0-V supply. Possible applications include clock and data recovery of a 10-Gb/s signal in a fiber-optic receiver as well as high-precision image rejection receivers and I/Q direct up-converters for radio-frequency applications.

Active substrate noise suppression in mixed-signal circuits using on-chip driven guard rings

This paper presents an active substrate noise suppression circuit using a pair of concentric guard rings. The outer guard ring senses the substrate noise, which is inverted and amplified by a SiGe circuit. This on-chip amplifier drives the inner guard ring such that efficient noise cancellation is achieved. A ring oscillator is used to sense the residual substrate noise. The measured noise suppression bandwidth is as high as 400 MHz.