Ashawant Gupta

Characterization of germanium implanted Si 1-x Ge x layer

Characterization of a Si1−xGex layer formed by high-dose germanium implantation and subsequent solid phase epitaxy is reported. Properties of this layer are obtained from electrical measurements on diodes and transistors fabricated in this layer. Results are compared with those of the silicon control devices. It was observed that the germanium implantation created considerable defects that are difficult to eliminate with annealing. These defects result in boron deactivation in the p-type regions of the devices, giving rise to larger resistance. Optimization of the device structure and fabrication process is discussed.

Properties of Schottky contacts of aluminum on strained Si1−x−yGexCy layers

Schottky contacts of Al/Si1−x−yGexCy were fabricated using conventional Si technology. Effects of thermal processing of the alloys on the electrical properties of the Al/Si1−x−yGexCy Schottky diodes were investigated. Current–voltage (I–V), capacitance–voltage (C–V), and x‐ray diffraction measurements were performed. These thick alloy films (100–150 nm) experienced strain relaxation upon annealing at 700 °C. Nearly ideal I–V and C–V behaviors were obtained for strain‐compensated samples. I–V and C–Vcharacteristics show evidence of dislocation‐related traps for strain‐relaxed samples. Carbon incorporation improves the I–V and C–V characteristics by lessening the extent of lattice relaxation due to thermal processing.

Donor complex formation due to a high‐dose Ge implant into Si

To investigate boron deactivation and/or donor complex formation due to a high‐dose Ge and C implantation and the subsequent solid phase epitaxy, SiGe and SiGeC layers were fabricated and characterized. Cross‐sectional transmission electron microscopy indicated that the SiGe layer with a peak Ge concentration of 5 at. % was strained; whereas, for higher concentrations, stacking faults were observed from the surface to the projected range of the Ge as a result of strain relaxation. Photoluminescence (PL) results were found to be consistent with dopant deactivation due to Ge implantation and the subsequent solid phase epitaxial growth of the amorphous layer. Furthermore, for unstrained SiGe layers (Ge peak concentration ≥7 at. %), the PL results support our previously proposed donor complex formation. These findings were confirmed by spreading resistance profiling. A model for donor complex formation is proposed.

Enhanced Degradation During Static Stressing of a Metal Oxide Semiconductor Field Effect Transistor Embedded in a Circuit

We have observed a unique phenomenon during low-gate voltage (V G) static stressing of metal-oxide-semiconductor-field-effect-transistors (MOSFETs). Static stressing has been performed by probing n-MOSFET devices that are discrete, as well as devices that are embedded in a circuit. Although the measured substrate current for the circuit and discrete devices is similar, significantly more hole trapping is observed under low-V G static stressing of circuit devices. It is clear that the extent of hole trapping is circuit dependent, and that in actual operation the devices will not undergo such static stressing. Nevertheless, these devices provided a unique opportunity to study the role of hole trapping in interface-state formation. Thus, rather than identifying the cause for increased hole trapping, we focused our efforts on understanding the mechanisms of interface-state formation. It is found that while both electrons and holes are needed for the formation of interface states, it is hole trapping that is the rate-limiting factor in device degradation.

Hole trapping as the rate-limiting factor in LDD nMOSFET degradation

We have observed a unique phenomenon during low-gate voltage (V/sub G/) static stressing of a CMOS circuit, that was designed for dynamic stressing. Static stressing was performed by probing 0.44 /spl mu/m lightly-doped-drain (LDD) nMOSFET devices that were discrete (isolated), as well as devices that were part of a circuit which consisted of a 301-stage BiCMOS ring-oscillator, followed by a chain of 6 inverters. Although the measured substrate currents (I/sub SUB/) for the circuit and discrete devices were quite similar, significantly more hole trapping was observed under low-V/sub G/ static stressing of circuit devices. It is clear that the extent of hole trapping is circuit dependent, and that in actual operation the devices would never undergo such static stressing. We focused our efforts on understanding the mechanisms of interface-state formation. Charge pumping (CP) measurements were used to confirm hole trapping and subsequent interface-state formation after each stress interval. The results were examined with the aid of the model proposed by Lai (1983), which states that interface state formation requires hole trapping followed by electron trapping. It was found that while both electrons and holes are needed for the formation of interface states, it is hole trapping that is the rate-limiting factor in device degradation.

Simulations of Ge and C Implantations to Form Si1-χGeχ BJT

Simulations of Ge and C implantations in Si were performed to study bandgap grading in the Si1-χGeχ bipolar junction transistor. It was found that a wide-bandgap emitter and a narrow-bandgap base with no discontinuity and desirable bandgap grading were obtainable with implantation. Hence compared to epitaxially grown heterojunction bipolar transistors, these devices are likely to result in better device reliability.

Formation of SiGe/Si Heterostructures by Low-Temperature Germanium Ion Implantation

Si1-xGex alloys were formed by high-dose (on the order of 1016 cm−2) germanium ion implantation into Si. It was found that the crystalline quality of the SiGe layer was improved by maintaining the substrate at low temperature during implantation. Cross-sectional transmission electron micrographs indicated a considerable reduction in the end-of-range defects. This improvement was further confirmed by electrical characterization of p-n junctions formed in the SiGe layer.

Characterization of Ge and C Implanted Si Diodes

Electrical characterization of diodes formed by Ge and C implantations in Si was performed. The results were compared with those obtained for a corresponding Si control device. Current-voltage measurements confirm that carbon doping improves the crystalline quality of the Ge-implanted SiGe layer. However, capacitance-voltage measurements indicate that carbon implantation causes significant dopant deactivation.