Kenichi Shoji

Characterization of SiGe/Si heterostructures formed by Ge+ and C+ implantation

Formation of SiGe/Si heterostructures by germanium ion implantation was investigated. A germanium‐implanted layer was grown epitaxially in the solid phase by thermal annealing. Two kinds of crystalline defects were observed. One is a misfit dislocation, and the other is a residual dislocation caused by ion bombardment. The p‐n junction formed in the SiGe layer has a leakage current three orders of magnitude larger than that of a pure Si p‐n junction fabricated with an identical process except for the Ge+ implantation. Carbon doping in the SiGe layer improves its crystalline quality and the junction characteristics.

Graded-bandgap SiGe Bipolar Transistor Fabricated with Germanium Ion Implantation

A graded-bandgap SiGe heterojunction bipolar transistor (HBT) is fabricated using Ge+ implantation. The maximum current gain and the maximum cutoff frequency are 40 and 8 GHz respectively, while those of the Si control device are 100 and 11 GHz. This relatively high cutoff frequency is obtained for the SiGe HBT despite considerable defects in the emitter and base regions, and is attributed to the drift field in the base region resulting from the graded bandgap.

Improved crystalline quality of Si1−xGex formed by low‐temperature germanium ion implantation

Improvement of crystalline quality in Si1−xGex formed by germanium ion implantation has been found. End‐of‐range defects were drastically reduced in number by lowering the substrate temperature during implantation with doses on the order of 1016 cm−2. This improvement was confirmed by electrical characterization of p‐n junctions formed in the SiGe layer as well as by transmission electron microscopy.

Characterization of germanium implanted Si 1-x Ge x layer

Characterization of a Si1−xGex layer formed by high-dose germanium implantation and subsequent solid phase epitaxy is reported. Properties of this layer are obtained from electrical measurements on diodes and transistors fabricated in this layer. Results are compared with those of the silicon control devices. It was observed that the germanium implantation created considerable defects that are difficult to eliminate with annealing. These defects result in boron deactivation in the p-type regions of the devices, giving rise to larger resistance. Optimization of the device structure and fabrication process is discussed.

Process and properties of Pt/Pb(Zr, Ti)O3/Pt integrated ferroelectric capacitors

Abstract A one-mask-patterned ferroelectric capacitor memory cell structures designed with a 0.5-μm feature size were fabricated. Oxygen plasma treatment after dry etching decreased the leakage current to as low as as-deposited film. The one-mask-patterned ferroelectric capacitors with switching charge almost equal to as-deposited film were achieved. Ferroelectric memories as dense as dynamic random access memories will become possible with this technology.

A 7.03-/spl mu/m/sup 2/ Vcc/2-plate nonvolatile DRAM cell with a Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etching

A ferroelectric memory cell with an area of only 7.03 /spl mu/m/sup 2/ designed with a 0.5-/spl mu/m rule has been fabricated. It performs Vcc/2-plate nonvolatile DRAM operation: ordinary DRAM operation and automatic nonvolatile writing when Vcc is shut down. A non-separated plate electrode and a capacitor patterned by one-mask dry etching reduce cell area. Planarization of the poly-Si plugs and the use of H-less metallization/passivation processes retain the PZT capacitor characteristics (Pr=50 fC/bit) and achieves ferroelectric write/read under /spl plusmn/2.5-V operation in 4-K bit memory cell arrays.

A scalable single-transistor/single-capacitor memory cell structure characterized by an angled-capacitor layout for megabit FeRAMs

A single-transistor/single-capacitor ferroelectric random access memory (FeRAM) cell having a cell size of 4.5 /spl mu/m/sup 2/ has been developed using 0.5-/spl mu/m technology. This cell features a stacked capacitor structure with a poly-Si plug and an angled-capacitor layout. This unique capacitor layout increases the alignment tolerance between the plate contact and the individual capacitor electrodes without increasing the cell area. O/sub 2/ annealing was applied after the plate-contact formation to restore the remanent polarization degradation. Favorable ferroelectric capacitor characteristics were observed when this cell was used in an experimental 4-Kbit memory-cell array.

Formation of SiGe/Si Heterostructures by Low-Temperature Germanium Ion Implantation

Si1-xGex alloys were formed by high-dose (on the order of 1016 cm−2) germanium ion implantation into Si. It was found that the crystalline quality of the SiGe layer was improved by maintaining the substrate at low temperature during implantation. Cross-sectional transmission electron micrographs indicated a considerable reduction in the end-of-range defects. This improvement was further confirmed by electrical characterization of p-n junctions formed in the SiGe layer.

Silicon Heterostructure by Germanium Ion Implantation

Formation of SiGe/Si heterostructure by germanium ion implantation and. subseguent solid phase epitaxy is investigated.. Two kind.s of crystalline defects are observed. one is a misfit dislocation and. the other is a residual dislocation caused by the ion bombard.ment. The p-n junction formed. in the SiGe layer has a leakage current three ord.ers of magnitud.e larger than that of a pure Si p-n junction. Carbon d.oping in the SiGe layer improves its crystalline quarity and the junctions characteristics.