Ashish Agrawal

A steep-slope transistor based on abrupt electronic phase transition

Collective interactions in functional materials can enable novel macroscopic properties like insulator-to-metal transitions. While implementing such materials into field-effect-transistor technology can potentially augment current state-of-the-art devices by providing unique routes to overcome their conventional limits, attempts to harness the insulator-to-metal transition for high-performance transistors have experienced little success. Here, we demonstrate a pathway for harnessing the abrupt resistivity transformation across the insulator-to-metal transition in vanadium dioxide (VO2), to design a hybrid-phase-transition field-effect transistor that exhibits gate controlled steep (‘sub-kT/q) and reversible switching at room temperature. The transistor design, wherein VO2 is implemented in series with the field-effect transistors source rather than into the channel, exploits negative differential resistance induced across the VO2 to create an internal amplifier that facilitates enhanced performance over a conventional field-effect transistor. Our approach enables low-voltage complementary n-type and p-type transistor operation as demonstrated here, and is applicable to other insulator-to-metal transition materials, offering tantalizing possibilities for energy-efficient logic and memory applications.

Experimental Staggered-Source and N+ Pocket-Doped Channel III--V Tunnel Field-Effect Transistors and Their Scalabilities

In this paper, we experimentally demonstrate 100% enhancement in drive current (ION) over In0.53Ga0.47As n-channel homojunction tunnel field-effect transistor (TFET) by replacing In0.53Ga0.47As source with a moderately staggered and lattice-matched GaAs0.5Sb0.5. The enhancement is also compared with In0.53Ga0.47As N+ pocket (δ)-doped channel homojunction TFET. Utilizing calibrated numerical simulations, we extract the effective scaling length (λeff) for the double gate, thin-body configuration of the staggered heterojunction and δ-doped channel TFETs. The extracted λeff is shown to be lower than the geometrical scaling length, particularly in the highly staggered-source heterojunction TFET due to the reduced channel side component of the tunnel junction width, resulting in improved device scalability.

Fermi level depinning and contact resistivity reduction using a reduced titania interlayer in n-silicon metal-insulator-semiconductor ohmic contacts

Experimental evidence of reduction of ultrathin TiO2 by Ti is presented and its effect on Fermi level depinning and contact resistivity reduction to Si is experimentally studied. A low effective barrier height of 0.15u2009V was measured with a Ti/10u2009A TiO2−x/n-Si MIS device, indicating 55% reduction compared to a metal/n-Si control contact. Ultra-low contact resistivity of 9.1u2009×u200910−9 Ω-cm2 was obtained using Ti/10u2009A TiO2−x/n+ Si, which is a dramatic 13X reduction from conventional unannealed contacts on heavily doped Si. Transport through the MIS device incorporating the effect of barrier height reduction and insulator conductivity as a function of insulator thickness is comprehensively analyzed and correlated with change in contact resistivity. Low effective barrier height, high substrate doping, and high conductivity interfacial layer are identified as key requirements to obtain low contact resistivity using MIS contacts.

A unified model for insulator selection to form ultra-low resistivity metal-insulator-semiconductor contacts to n-Si, n-Ge, and n-InGaAs

A comprehensive, physics-based unified model is developed for study of low resistivity metal-insulator-semiconductor (M-I-S) ohmic contact. Reduction in metal-induced gap state density and Fermi unpinning in semiconductor as a function of insulator thickness is coupled with electron transport including tunnel resistance through the metal-insulator-semiconductor (M-I-S) system to calculate specific contact resistivity at each insulator thickness for n-Si, n-Ge, and n-InGaAs. Low conduction band offset results in ∼1×10−9u2009Ω−cm2 contact resistivity with TiO2 insulator on n-Si, ∼7×10−9u2009Ω−cm2 can be achieved using TiO2 and ZnO on n-Ge, and ∼6×10−9u2009Ω−cm2 can be achieved with CdO insulator on n-InGaAs, which meet the sub-22nm CMOS requirements.

Experimental Determination of Quantum and Centroid Capacitance in Arsenide–Antimonide Quantum-Well MOSFETs Incorporating Nonparabolicity Effect

Experimental gate capacitance (<i>Cg</i>) versus gate voltage data for InAs_0.8Sb_0.2 quantum-well MOSFET (QW-MOSFET) is analyzed using a physics-based analytical model to obtain the quantum capacitance (<i>CQ</i>) and centroid capacitance (<i>C</i>_cent). The nonparabolic electronic band structure of the InAs_0.8Sb_0.2 QW is incorporated in the model. The effective mass extracted from Shubnikov-de Haas magnetotransport measurements is in excellent agreement with that extracted from capacitance measurements. Our analysis confirms that in the operational range of InAs_0.8Sb_0.2 QW-MOSFETs, quantization and nonparabolicity in the QW enhance <i>CQ</i> and <i>C</i>_cent. Our quantitative model also provides an accurate estimate of the various contributing factors toward <i>Cg</i> scaling in future arsenide-antimonide MOSFETs.

Enhancement-Mode Antimonide Quantum-Well MOSFETs With High Electron Mobility and Gigahertz Small-Signal Switching Performance

This letter demonstrates, for the first time, enhancement-mode (e-mode) antimonide MOSFETs by integrating a composite high-κ gate stack (3 nm Al₂O₃ -1 nm GaSb) with an ultrathin InAs_0.7Sb_0.3 quantum well (7.5 nm). The MOSFET exhibits record high electron drift mobility of 5200 cm²/V · s at carrier density (N_s) of 1.8 × 10¹² cm^-2, subthreshold slope of 150 mV/dec, I_ON/I_OFF ratio of ~4000× within a voltage window of ~1 V, high I_ON of 40 μA/μm at V_DS of 0.5 V for a 5-μm gate length (L_G) device. The device exhibits excellent pinchoff in the output characteristics with no evidence of impact ionization enabled by enhanced quantization and e-mode operation. RF characterization allows extraction of the intrinsic device metrics (C_gs, C_gd, g_m, v_eff and f_t) and the parasitic resistive and capacitive elements limiting the short-channel device performance.

Advanced composite high-κ gate stack for mixed anion arsenide-antimonide quantum well transistors

This paper demonstrates the integration of a composite high-κ gate stack (3.3 nm Al<inf>2</inf>O<inf>3</inf>−1.0 nm GaSb) with a mixed anion InAs<inf>0.8</inf>Sb<inf>0.2</inf> quantum-well field effect transistor (QWFET). The composite gate stack achieves; (i) EOT of 4.2 nm with &#60;10⁻⁷A/cm² gate leakage (ii) low D<inf>it</inf> interface (∼1×10¹² /cm²/eV) (iii) high drift µ of 3,900–5,060 cm²/V-s at N<inf>S</inf> of 5×10¹¹−3×10¹²/cm². The InAs<inf>0.8</inf>Sb<inf>0.2</inf> MOS-QWFETs with composite gate stack exhibit extrinsic (intrinsic) g<inf>m</inf> of 334 (502) µS/µm and drive current of 380 µA/µm at V<inf>DS</inf> = 0.5V for Lg=1µm.

Impact of contact and local interconnect scaling on logic performance

We perform a comparative analysis of metal-Si and metal-insulator-Si (MIS) contacts and quantify the impact of the contact/via resistances on logic performance. Our results show that silicide contacts account for 32% degradation in the ON current of an nFinFET (ION) compared to ideal contact. MIS contacts which lead to lowering of Schottky barrier height provide 12% performance gain at iso-energy. Technology scaling to 5 nm will make MIS contact contribute 35% to the overall extrinsic resistance, with metal resistance contribution rising to 20%.

In Situ Process Control of Trilayer Gate-Stacks on p-Germanium With 0.85-nm EOT

In situ spectroscopic ellipsometry was utilized in an atomic-layer-deposition (ALD) reactor for rapid and rational gate stack process optimization of the trilayer dielectric HfO₂/Al₂O₃/GeO_x on Ge. The benefit of this approach was demonstrated by developing an entire process in situ: 1) native oxide removal by hydrogen plasma; 2) controlled reoxidation for Ge surface passivation; and 3) deposition of Al₂O₃ and HfO₂ using thermal ALD. The low-k layer thicknesses were scaled down without losing their respective functions, i.e., GeO_x to form an electrically well behaved interface with Ge and Al₂O₃ to thermodynamically stabilize the GeO_x/Ge interface. Aggressive equivalent-oxide-thickness scaling of the trilayer stack down to 0.85 nm with a low gate leakage of 0.15 mA/cm² at V_FB- 1 V was achieved, while preserving a high-quality dielectric-semiconductor interface.

Compressively strained InSb MOSFETs with high hole mobility for p-channel application

We demonstrate synthesis of p-channel InSb MOSFET with 1.9% compressive biaxial strain with outstanding room temperature and 150K Hall mobility of 680 cm2/Vs and 2,500 cm2/Vs at hole sheet density of 5x1012 /cm2 and 2.3x1012 /cm2, respectively. The incorporation of an InP layer on top of Al0.35In0.65Sb barrier allows for integration of a high-k dielectric and demonstration of InSb pMOSFET with significantly reduced gate leakage. Parallel conduction limits the on-off ratio of the InSb MOSFET above 150K. Refinement of the InP barrier to reduce interface states and buffer layer to reduce parallel conduction is expected to improve InSb pMOSFET characteristics at 300K.