Dmitri Loubychev

Ultrahigh-Speed 0.5 V Supply Voltage

The direct epitaxial growth of ultrahigh-mobility InGaAs/InAlAs quantum-well (QW) device layers onto silicon substrates using metamorphic buffer layers is demonstrated for the first time. In this letter, 80 nm physical gate length depletion-mode InGaAs QW transistors with saturated transconductance gm of 930 muS / mum and fT of 260 GHz at VDS = 0.5 V are achieved on 3.2 mum thick buffers. We expect that compound semiconductor-based advanced QW transistors could become available in the future as very high-speed and ultralow-power device technology for heterogeneous integration with the mainstream silicon CMOS.

\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}

In this paper, we experimentally demonstrate 100% enhancement in drive current (ION) over In0.53Ga0.47As n-channel homojunction tunnel field-effect transistor (TFET) by replacing In0.53Ga0.47As source with a moderately staggered and lattice-matched GaAs0.5Sb0.5. The enhancement is also compared with In0.53Ga0.47As N+ pocket (δ)-doped channel homojunction TFET. Utilizing calibrated numerical simulations, we extract the effective scaling length (λeff) for the double gate, thin-body configuration of the staggered heterojunction and δ-doped channel TFETs. The extracted λeff is shown to be lower than the geometrical scaling length, particularly in the highly staggered-source heterojunction TFET due to the reduced channel side component of the tunnel junction width, resulting in improved device scalability.

Quantum-Well Transistors on Silicon Substrate

Type II arsenide/antimonide compound semiconductor with highly staggered GaAs<inf>0.35</inf>Sb<inf>0.65</inf>/In<inf>0.7</inf>Ga<inf>0.3</inf>As hetero-junction is used to demonstrate hetero tunnel FET (TFET) with record high drive currents (I<inf>ON</inf>) of 190µA/µm and 100µA/µm at V<inf>DS</inf>=0.75V and 0.3V, respectively (L<inf>G</inf>=150nm). In<inf>x</inf>Ga<inf>1−x</inf>As (x=0.53, 0.7) homo-junction TFETs and GaAs<inf>0.5</inf>Sb<inf>0.5</inf>/In<inf>0.53</inf>Ga<inf>0.47</inf>As hetero TFET with moderate stagger are also fabricated with the same process flow for benchmarking. Measured and simulated TFET performance is benchmarked with 40nm strained Si MOS-FETs for 300mV logic applications.

Experimental Staggered-Source and N+ Pocket-Doped Channel III--V Tunnel Field-Effect Transistors and Their Scalabilities

Staggered tunnel junction (GaAs_0.35Sb_0.65/In_0.7Ga_0.3As) is used to demonstrate heterojunction tunnel FET (TFET) with the highest drive current, I_on, of 135μA/μm and highest I_on/I_off ratio of 2.7×10⁴ (V_ds=0.5V, V_on-V_off=1.5V). Effective oxide thickness (EOT) scaling (using Al₂O₃/HfO₂ bilayer gate stack) coupled with pulsed I-V measurements (suppressing D_it response) enable demonstration of steeper switching TFET.

Demonstration of MOSFET-like on-current performance in arsenide/antimonide tunnel FETs with staggered hetero-junctions for 300mV logic applications

We report InP/InGaAs/InP double heterojunction bipolar transistors (DHBT) fabricated using a simple mesa structure. The devices employ a 30 nm highly doped InGaAs base and a 150 nm InP collector containing an InGaAs/InAlAs superlattice grade. These devices exhibit a maximum f_max = 755 GHz with a 416 GHz /f_T. This is the highest f_max reported for a mesa HBT. Through the use of i-line lithography, the emitter junctions have been scaled from 500-600 nm down to 250-300 nm -all while maintaining similar collector to emitter area ratios. Because of the subsequent reduction to the base spreading resistance underneath the emitter R_b,spread and increased radial heat flow from the narrower junction, significant increases to f_max and reductions in device thermal resistance θ_JA are expected and observed. The HBT current gain β ≈ 24-35, BV_ceo = 4.60 V, BV_cbo = 5.34 V, and the devices operate up to 20 mW / μm² before self-heating is observed to affect the DC characteristics.

Demonstration of improved heteroepitaxy, scaled gate stack and reduced interface states enabling heterojunction tunnel FETs with high drive current and high on-off ratio

InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBT) have been designed for increased bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 450 GHz f/sub /spl tau// and 490 GHz f/sub max/, which is the highest simultaneous f/sub /spl tau// and f/sub max/ for any HBT. The devices have been scaled vertically for reduced electron collector transit time and aggressively scaled laterally to minimize the base-collector capacitance associated with thinner collectors. The dc current gain /spl beta/ is /spl ap/ 40 and V/sub BR,CEO/=3.9 V. The devices operate up to 25 mW//spl mu/m/sup 2/ dissipation (failing at J/sub e/=10 mA//spl mu/m/sup 2/, V/sub ce/=2.5 V, /spl Delta/T/sub failure/=301 K) and there is no evidence of current blocking up to J/sub e//spl ges/12 mA//spl mu/m/sup 2/ at V/sub ce/=2.0 V from the base-collector grade. The devices reported here employ a 30-nm highly doped InGaAs base, and a 120-nm collector containing an InGaAs/InAlAs superlattice grade at the base-collector junction.

Sub-300 nm InGaAs/InP Type-I DHBTs with a 150 nm collector, 30 nm base demonstrating 755 GHz f max and 416 GHz f T

Abstract-We report an InPZIn_0.53Ga_0.47As/InP double heterojunction bipolar transistor (DHBT) demonstrating simultaneous 430-GHz f_τ and 800-GHz f_max. The devices were fabricated using a triple mesa process with dry-etched refractory metals for emitter contact formation. The devices incorporate a 30-nm-thick InP emitter semiconductor which enables a wet-etch emitter process demonstrating 270-nm-wide emitter-base junctions. At peak RF performance, the device is operating at 30 mW/μm² with J_c = 18.4 mA/μm² and V_ce = 1.64 V. The devices show a peak DC common-emitter current gain (β) ~ 20 and V_BR,CEO = 2.5 V.

InGaAs/InP DHBTs with 120-nm collector having simultaneously high f/sub /spl tau//, f/sub max//spl ges/450 GHz

We report 220 nm InP double heterojunction bipolar transistors (DHBTs) demonstrating f<inf>τ</inf> = 480 GHz and f<inf>max</inf> = 1.0 THz. Improvements in the emitter and base processes have made it possible to achieve a 1.0 THz f<inf>max</inf> even at 220 nm wide emitter-base junction with a 1.1 µm wide base-collector mesa. A vertical emitter metal etch profile, wet-etched thin InP emitter semiconductor with less than 10 nm undercut and self-aligned base contact deposition reduces the emitter semiconductor-base metal gap (W<inf>gap</inf>) to ∼ 10 nm, thereby significantly reducing the gap resistance term (R<inf>gap</inf>) in the total base access resistance (R<inf>bb</inf>), enabling a high f<inf>max</inf> device. Reduction in the total collector base capacitance (C<inf>cb</inf>) through undercut in the base mesa below base post further improved f<inf>max</inf>. These devices employ a Mo/W/TiW refractory emitter metal contact which allows biasing the transistors at high emitter current densities (J<inf>e</inf>) without problems of electromigration or contact diffusion under electrical stress [1].

InGaAs/InP DHBTs in a Dry-Etched Refractory Metal Emitter Process Demonstrating Simultaneous

Type I InP/InGaAs/InP double heterojunction bipolar transistors were fabricated using a simple mesa structure, where emitter junction widths have been scaled from 250 nm to 200 nm. These devices exhibit ƒ<inf>max</inf> in excess of 800 GHz, and ƒ<inf>τ</inf> = 360 GHz. Greater than fifty percent device yield was obtained by employing two 25 nm SiN<inf>x</inf> sidewalls to protect and anchor the refractory metal emitter contact to the emitter semiconductor. A hybrid dry and wet etch process is used to form a vertical emitter mesa, causing reductions in both the emitter-base gap resistance R<inf>gap</inf> and the spreading resistance beneath the emitter R<inf>b,spread</inf>, leading to an expected and observed increase in ƒ<inf>max</inf>. Peak HBT current gains β ≈ 21–33, BV<inf>ceo</inf> ∼ 4 V, BV<inf>cbo</inf> ∼ 5 V, and J<inf>e</inf> at low V<inf>cb</inf> is over 10 mA/μm².

f_{\tau}/f_{\max} \sim \hbox{430/800}\ \hbox{GHz}

This letter reports InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBTs) employing an N/sup +/ subcollector and N/sup +/ collector pedestal-formed by blanket Fe and patterned Si ion implants, intended to reduce the extrinsic collector-base capacitance C/sub cb/ associated with the device footprint. The Fe implant is used to compensate Si within the upper 130 nm of the N/sup +/ subcollector that lies underneath the base ohmic contact, as well as compensate the /spl sim/1-7/spl times/10/sup -7/ C/cm/sup 2/ surface charge at the interface between the indium phosphide (InP) substrate and the N/sup