Ashish Raman

Low power ALU design by ancient mathematics

The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip. Still the load on the processor is not less in generic system. This load is reduced by supplementing the main processor with Co-Processors, which are designed to work upon specific type of functions like numeric computation, Signal Processing, Graphics etc. The speed of ALU depends greatly on the multiplier Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. Employing these techniques in the computation algorithms of the coprocessor will reduce the complexity, execution time, area, power etc. The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip. Still the load on the processor is not less in generic system. This load is reduced by supplementing the main processor with Co-Processors, which are designed to work upon specific type of functions like numeric computation, Signal Processing, Graphics etc. The speed of ALU depends greatly on the multiplier Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. Employing these techniques in the computation algorithms of the coprocessor will reduce the complexity, execution time, area, power etc.

Small area reconfigurable FFT design by Vedic Mathematics

The Fast Fourier Transform (FFT)is a computationally intensive digital signal processing(DSP)function widely used in applications such as imaging, software-defined radio, wireless communication, instrumentation and machine inspection. Historically, this has been a relatively difficult function to implement optimally in hardware leading many software designers to use digital signal processors in soft implementations. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. Employing these techniques in the computation algorithms of the coprocessor will reduce the complexity, execution time, area, power etc. In this paper reconfigurable FFT is proposed to design by Vedic mathematics. Urdhva tiryakbhyam, being a general multiplication formula, is equally applicable to all cases of multiplication. Nikhilam algorithm with the compatibility to different data types.

Distance Based Enhanced Threshold Sensitive Stable Election Routing Protocol for Heterogeneous Wireless Sensor Network

The technological advancements have led to the revolution in sensing technology. Wireless Sensor Network (WSN) has been one of the important researched areas which have attracted attention of various researchers. The battery constraints have led to the development of energy efficient routing protocols. Past studies ignore the importance of distance factor for the selection of Cluster Head (CH), which led to inefficient energy consumption in the network. In this chapter, Distance based Enhance Threshold Sensitive Stable Election Protocol (DETSSEP) has been proposed in which CH selection is based on networks average energy, nodes remaining energy and distance between nodes and Base Station (BS). Dual hop communication is used between distant CHs and BS to achieve uniform energy consumption in the network. It is observed through the simulation analysis that DETSSEP outperforms Enhance Threshold Sensitive Stable Election Protocol (ETSSEP) in various performance matrices viz. stability period, throughput, lifetime and remaining energy of the network.

Design and optimization analysis of dual material gate on DG-IMOS

An impact ionization MOSFET (IMOS) is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope (SS) of conventional MOSFET at room temperature. In this work, first, the device performance of the p-type double gate impact ionization MOSFET (DG-IMOS) is optimized by adjusting the device design parameters. The adjusted parameters are ratio of gate and intrinsic length, gate dielectric thickness and gate work function. Secondly, the DMG (dual material gate) DG-IMOS is proposed and investigated. This DMG DG-IMOS is further optimized to obtain the best possible performance parameters. Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS, shows better I ON , I ON / I OFF ratio, and RF parameters. Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS, optimized performance is achieved including I ON / I OFF ratio of 2.87 × 10 9 A/ μ m with I ON as 11.87 × 10 −4 A/ μ m and transconductance of 1.06×10 −3 S/ μ m. It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.

Design and analysis of RF-low power and low-phase noise CMOS ring oscillator for fully integrated RF communication systems technologies

This manuscript presents the design and analysis of five-stage, low power ring oscillator. The ring oscillator has implemented in 0.18 µm CMOS one-poly six-metal-layer process technology and designed for frequency synthesiser module used in RF communication applications. This work uses a single ended topology and the delay cell is designed with both tail-ahead and tail-current concept for frequency improvement. This work projects the effect of transistor size w/l on the important parameters of oscillator viz. frequency and power dissipation. Measurements show that the oscillator covers a frequency range of 0.9-2 GHz. Their analyses demonstrate that the circuit consumes minimum power of 305 µW at 0.9 GHz and maximum 575 µW at 2 GHz oscillating frequency. The designed oscillator occupies an area of 296 * 130 µm² and manifest an improved phase noise level of −111.9 dBc/Hz.

The design of a novel delay cell based 8.3 GHz, low phase noise ring oscillator in C-MOS 180 nm technology for biomedical ultra-wide-band integrated applications

This paper presents the designing of a novel wide frequency range, low phase noise, 3-delay stages based ring oscillator for Ultra-Wide-Band (UWB) biomedical application. The phase noise is reduced by using both PMOS and NMOS latch together. The high frequency is achieved, reducing the switching time of the delay cell, varying the resistance through control voltage (VCONTROL), controlling the strength of the NMOS latch through tuning voltage (VTUNE) and by connecting the gates of the secondary input transistor with same input of the delay cell. This oscillator is implemented using 180 nm CMOS process provided by TSMC. The designed oscillator is measured to cover a frequency range of 5.9–8.3 GHz@1.8-V power supply and manifests a phase noise of –167dBc/Hz @1MHz and –175 dBc/Hz @10 MHz offset from a centre frequency of 5.9 GHz and occupies an area of 194 μm × 147 μm with the power dissipation of 14.684 dbm.