R. K. Sarin

Small area reconfigurable FFT design by Vedic Mathematics

The Fast Fourier Transform (FFT)is a computationally intensive digital signal processing(DSP)function widely used in applications such as imaging, software-defined radio, wireless communication, instrumentation and machine inspection. Historically, this has been a relatively difficult function to implement optimally in hardware leading many software designers to use digital signal processors in soft implementations. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. Employing these techniques in the computation algorithms of the coprocessor will reduce the complexity, execution time, area, power etc. In this paper reconfigurable FFT is proposed to design by Vedic mathematics. Urdhva tiryakbhyam, being a general multiplication formula, is equally applicable to all cases of multiplication. Nikhilam algorithm with the compatibility to different data types.

Performance analysis of charge plasma based dual electrode tunnel FET

This paper proposes the charge plasma based dual electrode doping-less tunnel FET (DEDLTFET). The paper compares the device performance of the conventional doping-less TFET (DLTFET) and doped TFET (DGTFET). DEDLTEFT gives the superior results with high ON state current (ION ~ 0.56 mA/μm), ION/IOFF ratio ~ 9.12 × 1013 and an average subthreshold swing (AV-SS ~ 48 mV/dec). The variation of different device parameters such as channel length, gate oxide material, gate oxide thickness, silicon thickness, gate work function and temperature variation are done and compared with DLTFET and DGTFET. Through the extensive analysis it is found that DEDLTFET shows the better performance than the other two devices, which gives the indication for an excellent future in low power applications.

Compact corner truncated triangular patch antenna for WiMax application

The design of a small short-circuited triangular patch antenna with truncated corner has been introduced. By placing two shorting walls with a V-shaped slot patch, two resonant modes can be excited simultaneously. This antenna structure has been designed for covering (2.5–2.55GHz) and (3.4 to 3.7 GHz) WiMax bands. A substrate of low dielectric constant is selected to obtain a compact radiating structure that meets the demanding bandwidth specification. The reflection coefficient at the input of the optimized V-shaped microstrip patch antenna is below −10 dB over the entire frequency band. The simulation is carried out by EMPIRE XCcel software.

Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

In this paper, charge-plasma-based tunnel FET is proposed by employing dual material gate with hetero gate dielectric technique and it is named hetero-dielectric dual material gate doping-less TFET(HD_DMG_DLTFET). It is compared with conventional doping-less TFET(DLTFET) and dual material gate doping-less TFET(DMG_DLTFET) on the basis of analog and RF performance. The HD_DMG_DLTFET provides better ON state current(ION=94 μA/μm), ION/IOFF(≈ 1:36×1013), point(≈ 3 mV/dec) and average subthreshold slope(AV-SS=40.40 mV/dec). The proposed device offers low total gate capacitance(Cgg)along with higher drive current. However, with a better transconductance(gm) and cut-off frequency(fT), the HD_DMG_DLTFET can be a good candidate for RF circuitry. The early voltage(VEA) and output conductance(gd) are also moderate for the proposed device with comparison to other devices and therefore can be a candidate for analog devices. From all these simulation results and their study, it is observed that HD_DMG_DLTFET has improved analog/RF performance compared to DLTFET and DMG_DLTFET.

Comparison of thermometer to binary encoders for flash ADCs

Encoders play a critical role in performance of analog to digital converters (ADCs). These encoders can be implemented in different topologies depending upon the required performance ADCs. In this paper different thermometer to binary (T2B) encoders employed in flash ADCs are analyzed in terms of bubble error, delay and power consumption. ROM encoder, Wallace tree, Fat tree and Multiplexer based encoder are compared for their performance.

Analog realization of fuzzifier for IT2 fuzzy processor

In this paper, design of CMOS based fuzzifier block for a general purpose Interval type-2 fuzzy processor is presented. The fuzzifier generates the Footprints of Uncertainty (FOU) for the input variables. It can implement four basic membership functions (MFs) viz. Z, trapezoidal, triangle and S. The characteristics (width, slope, position) of the lower and upper bounds of the FOU are easily adjustable. The simulations of the fuzzifier have been carried out by the Spectre tool of Cadence and the proposed design has been implemented for a two inputs function each having three MFs on 0.18um technology using Cadence Virtuoso Schematic/Layout Editor. Power consumption of the fuzzifier is 2.64mW and it occupies an area of 0.006mm.

Effect of Photonic Band Gap structure on Planar Antenna configuration

This paper describes the effect of Photonic Band Gap (PBG) structure as ground plane coupled with defected ground plane on Planar Antenna using coplanar waveguide with improvement of bandwidth and return loss value of 50% (in case of array of 3 × 5 UC-PBG) and 6.45 dB at resonant frequency of 3.6 GHz and is used for WIMax band (3.3 GHz to 3.8GHz) for Wireless Local Area Network (WLAN) applications.

Design and analysis of area efficient QCA based reversible logic gates

Abstract The CMOS technology has been plagued by several problems in past one decade. The ever increasing power dissipation is the major problem in CMOS circuits and systems. The reversible computing has potential to overcome this problem and reversible logic circuits serve as the backbone in quantum computing. The reversible computing also offers fault diagnostic features. Quantum-dot cellular automata (QCA) nanotechnology owing to its unique features like very high operating frequency, extremely low power dissipation, and nanoscale feature size is emerging as a promising candidate to replace CMOS technology. This paper presents design and performance analysis of area efficient QCA based Feynman, Toffoli, and Fredkin universal reversible logic gates. The proposed designs of QCA reversible Feynman, Toffoli, and Fredkin reversible gates utilize 39.62, 21.05, and 24.74% less number of QCA cells as compared to previous best designs. The rectangular layout area of proposed QCA based Feynman, Toffoli, and Fredkin gates are 52, 28.10, and 40.23%, respectively less than previous best designs. The optimized designs are realized employing 5-input majority gates to make proposed designs more compact and area efficient. The major advantage is that the optimized layouts of reversible gates did not utilize any rotated, translated QCA cells, and offer single layer accessibility to their inputs and outputs. The proposed efficient layouts did not employ any coplanar or multi-layer wire crossovers. The energy dissipation results have been computed for proposed area efficient reversible gates and thermal layouts are generated using accurate QCAPro power estimator tool. The functionality of presented designs has been performed in QCADesigner version 2.0.3 tool.

Analysis of Interpolated FIR Filter for VoIP in Noisy Enviroment

The presence of background noise degrades the quality of speech signal. The speech quality of the VoIP system can be improved by reducing the background noise, codec distortion and various network impairments such as packet loss, delay and jitter. The work in this paper proposes the Interpolated Finite Impulse Response filter (IFIR) based scheme for reduction of noise. The IFIR filter would be applied as post processing after the speech decoding. For various noisy conditions, the quality of speech signal is measured with PESQ measurement to evaluate the performance of the proposed method. The codec tested with proposed method are G.729A and AMR-NB. The performance is evaluated not only for the codec used but also for VoIP system with packet loss in noisy environment. The results show much improvement in speech quality with proposed method

The impact of gate misalignment on the analog performance of a dual-material double gate junctionless transistor

The analog performance of gate misaligned dual material double gate junctionless transistor is demonstrated for the first time. The cases considered are where misalignment occurs towards source side and towards drain side. The analog performance parameters analyzed are: transconductance, output conductance, intrinsic gain and cut-off frequency. These figures of merits (FOMs) are compared with a dual material double gate inversion mode transistor under same gate misalignment condition. The impacts of different length of control gate (L1) for a given gate length (L) are also studied and the optimum lengths L1 under misalignment condition to have better analog FOMs and high tolerance to misalignment are presented.