Ashkan Roshan-Zamir

A 40 Gb/s PAM4 silicon microring resonator modulator transmitter in 65nm CMOS

A silicon photonic microring resonator modulator transmitter utilizes a segmented pulsed-cascode output stage for voltage level control to achieve PAM4 modulation on a single microring device. The 65nm CMOS transmitter achieves 40Gb/s operation at 3.04mW/Gb/s when driving depletion-mode microring modulators with 4.4Vppd swing.

PAM4 silicon photonic microring resonator-based transceiver circuits

Increased data rates have motivated the investigation of advanced modulation schemes, such as four-level pulseamplitude modulation (PAM4), in optical interconnect systems in order to enable longer transmission distances and operation with reduced circuit bandwidth relative to non-return-to-zero (NRZ) modulation. Employing this modulation scheme in interconnect architectures based on high-Q silicon photonic microring resonator devices, which occupy small area and allow for inherent wavelength-division multiplexing (WDM), offers a promising solution to address the dramatic increase in datacenter and high-performance computing system I/O bandwidth demands. Two ring modulator device structures are proposed for PAM4 modulation, including a single phase shifter segment device driven with a multi-level PAM4 transmitter and a two-segment device driven by two simple NRZ (MSB/LSB) transmitters. Transmitter circuits which utilize segmented pulsed-cascode high swing output stages are presented for both device structures. Output stage segmentation is utilized in the single-segment device design for PAM4 voltage level control, while in the two-segment design it is used for both independent MSB/LSB voltage levels and impedance control for output eye skew compensation. The 65nm CMOS transmitters supply a 4.4Vppd output swing for 40Gb/s operation when driving depletion-mode microring modulators implemented in a 130nm SOI process, with the single- and two-segment designs achieving 3.04 and 4.38mW/Gb/s, respectively. A PAM4 optical receiver front-end is also described which employs a large input-stage feedback resistor transimpedance amplifier (TIA) cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity. Receiver linearity, critical in PAM4 systems, is achieved with a peak-detector-based automatic gain control (AGC) loop.

A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS

While four-level pulse amplitude modulation (PAM4) standards are emerging to increase bandwidth density, the majority of standards use simple binary non-return-to-zero (NRZ) signaling. This paper presents a dual-mode NRZ/PAM4 serial I/O SerDes which can support both modulations with minimum power and hardware overhead relative to a dedicated PAM4 link. A source-series-terminated transmitter achieves 1.2-

A 40Gb/s PAM4 optical DAC silicon microring resonator modulator transmitter

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A two-segment optical DAC 40 Gb/s PAM4 silicon microring resonator modulator transmitter in 65nm CMOS

output swing and employs lookup table control of a 31-segment output digital-to-analog converter (DAC) to implement 4/2-tap feed-forward equalization in NRZ/PAM4 modes, respectively. Transmitter power is improved with low-overhead analog impedance control in the DAC cells and a quarter-rate serializer based on a tri-state inverter-based mux with dynamic pre-driver gates. The receiver implements an NRZ/PAM4 decision feedback equalizer that employs one finite impulse response and two infinite impulse response taps for first post-cursor and long-tail inter-symbol interference (ISI) cancellation, respectively. First post-cursor ISI cancellation is performed in these comparators to optimize the design’s timing, while the remaining ISI taps are subtracted in a preceding current integration summer for improved sensitivity. Fabricated in GP 65-nm CMOS, the transceiver occupies 0.074 mm2 area and achieves 16 Gb/s NRZ and 32 Gb/s PAM4 operation at 10.9 and 5.5 mW/Gb/s while operating over channels with 27.6 and 13.5 dB loss at Nyquist, respectively.

A 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65nm CMOS

PAM4 modulation is currently being implemented in high-speed wireline communication standards in order to increase bandwidth density. This paper presents a transmitter which utilizes a low-area silicon microring resonator modulator with two separate phase shifter segments to realize high-speed PAM4 modulation with an optical DAC approach. The optical DAC is designed with an optimized MSB/LSB segment size ratio of 1.9:1 to generate a uniform four level output with independent MSB/LSB two-level NRZ drivers. Two differential high-swing segmented pulsed-cascode output stages drive the MSB/LSB segments with independent edge-rate and level controls that compensate for output level spacing and eye skew. The hybrid integrated prototype, with the optical DAC microring modulator fabricated in a 130nm silicon photonic process and the transmitter circuitry fabricated in a GP 65nm CMOS process, achieves 40Gb/s operation at 4.38mW/Gb/s when driving each differential terminal of the segmented depletion-mode microring modulator with 4.4Vppd swing.

A 32 Gb/s 0.55 mW/Gbps PAM4 1-FIR 2-IIR tap DFE receiver in 65-nm CMOS

A two-segment silicon photonic microring modulator implements an optical DAC for PAM4 modulation. Independent level and edge-rate control is achieved using segmented MSB/LSB pulsed-cascode drivers. The 65nm CMOS transmitter achieves 40Gb/s operation at 4.38mW/Gb/s while driving each microring modulator segment with 4.4Vppd swing.

A Fully-integrated Multi-λ Hybrid DML Transmitter

A dual-mode NRZ/PAM4 SerDes seamlessly supports both modulations with a 1-FIR- and 2-IIR-tap DFE receiver and a 4/2-tap FFE transmitter in NRZ/PAM4 modes, respectively. A source-series-terminated (SST) transmitter employs lookup-table (LUT) control of a 31-segment output DAC to implement FFE equalization in NRZ and PAM4 modes with 1.2 Vpp output swing and utilizes low-overhead analog impedance control. Optimization of the quarter-rate transmitter serializer is achieved with a tri-state inverter-based mux with dynamic pre-driver gates. The quarter-rate DFE receiver achieves efficient equalization with 1-FIR tap for the large first post-cursor ISI and 2-IIR taps for long-tail ISI cancellation. Fabricated in GP 65-nm CMOS, the transceiver occupies 0.074 mm2 area and achieves power efficiencies of 10.9 and 5.5 mW/Gbps with 16 Gb/s NRZ and 32 Gb/s PAM4 data, respectively.