Kunzhi Yu

A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS

Silicon photonics devices offer promising solution to meet the growing bandwidth demands of next-generation interconnects. This paper presents a 5 × 25 Gb/s carrier-depletion microring-based wavelength-division multiplexing (WDM) transmitter in 65 nm CMOS. An AC-coupled differential driver is proposed to realize 4 × VDD output swing as well as tunable DC-biasing. The proposed transmitter incorporates 2-tap asymmetric pre-emphasis to effectively cancel the optical nonlinearity of the ring modulator. An average-power-based dynamic wavelength stabilization loop is also demonstrated to compensate for thermal induced resonant wavelength drift. At 25 Gb/s operation, each transmitter channel consumes 113.5 mW and maintains 7 dB extinction ratio with a 4.4 V pp-diff output swing in the presence of thermal fluctuations.

22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization

Wavelength-division multiplexing (WDM) optical interconnect architectures based on microring resonator devices offer a low-area and energy-efficient approach to realize both high-speed modulation and WDM with high-speed transmit-side ring modulators and high-Q receive-side drop filters [1-3]. While CMOS optical front-ends have been previously developed that support data-rates in excess of 20Gb/s, these designs often do not offer the retiming and deserialization functions required to form a complete link [1,4]. Furthermore, along with the requirements of a sensitive energy-efficient receiver front-end with low-complexity clocking, wavelength stabilization control is necessary to compensate for the fabrication tolerances and thermal sensitivity of microring drop filters. In this work, a 24Gb/s hybrid-integrated microring receiver is demonstrated the incorporates the following key advances: 1) a low-complexity optically-clocked source-synchronous receiver with LC injection-locked oscillator (ILO) jitter filtering; 2) a large input-stage feedback resistor TIA cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity and bandwidth; 3) a receive-side thermal tuning loop that stabilizes the microring drop filter resonance wavelength with minimal impact on receiver sensitivity.

A 40 Gb/s PAM4 silicon microring resonator modulator transmitter in 65nm CMOS

A silicon photonic microring resonator modulator transmitter utilizes a segmented pulsed-cascode output stage for voltage level control to achieve PAM4 modulation on a single microring device. The 65nm CMOS transmitter achieves 40Gb/s operation at 3.04mW/Gb/s when driving depletion-mode microring modulators with 4.4Vppd swing.

25Gb/s hybrid-integrated silicon photonic receiver with microring wavelength stabilization

A 25Gb/s hybrid-integrated microring receiver which includes a thermal tuning loop that stabilizes the drop filter resonance wavelength is implemented. The multi-channel 65nm CMOS source-synchronous receiver achieves -8.2 dBm sensitivity at BER <;10-12 and 0.68pJ/b.

22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS

Silicon photonic microring modulators (MRMs) offer a promising approach for realizing energy-efficient wavelength-division multiplexing (WDM) optical interconnects. For data-rates greater than 10Gb/s, depletion-mode MRMs are generally preferred over their injection-mode counterparts due to their shorter carrier lifetimes and resulting higher bandwidths. Unfortunately, these depletion-mode MRMs typically exhibit low PN junction tunability, thereby requiring higher modulation voltages in order to provide >6dB extinction ratios (ER). Furthermore, negative DC-biasing of the MRMs is necessary to maintain reverse-biased depletion-mode operation. In this work, a 5×25Gb/s hybrid-integrated MRM WDM transmitter is demonstrated that incorporates the following key advances: 1) an AC-coupled differential output driver that applies a 4.4Vpp-diff output-swing on the MRM while providing a tunable on-chip negative DC-bias; 2) a 2-tap non-linear digital FFE that compensates for optical-dynamics-induced bandwidth limitations; 3) a dynamic thermal tuning loop that stabilizes the MRM by minimizing thermally-induced wavelength fluctuations.

25 Gbps low-voltage waveguide Si–Ge avalanche photodiode

We demonstrate a waveguide Si-Ge avalanche photodiode with a breakdown voltage of -10V, a speed of 25GHz, and a gain-bandwidth product of 276GHz. The APD optical receiver achieved sensitivities of -25dBm and -16dBm at 12.5Gbps and 25Gbps at 1550nm, respectively.

Energy efficiency comparisons of NRZ and PAM4 modulation for ring-resonator-based silicon photonic links

Advanced modulation schemes, such as PAM4, are currently under consideration in both high-speed electrical and optical interconnect systems. This paper analyzes how NRZ and PAM4 modulation impacts the energy efficiency of an optical link architecture based on silicon photonic microring resonator modulators and drop filters, and how this changes as CMOS technology scales from a 65nm to a 16nm node. Two ring modulator device structures are proposed for PAM4 modulation, including a single-segment device driven with a multi-level PAM4 transmitter and a two-segment device driven by two simple NRZ (MSB/LSB) transmitters. Modeling results with carrier-depletion ring modulators and transmitter driver and receiver circuitry show that the PAM4 architectures achieve superior energy efficiency at higher data rates due to the relaxed circuit bandwidth, with the cross-over point scaling from 30Gb/s in the 65nm node to 50Gb/s in the 16nm node.

DWDM silicon photonic transceivers for optical interconnect

We present energy-efficient microring resonator-based silicon photonic transceivers for DWDM optical interconnect.

A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization

Single-mode wavelength-division multiplexing (WDM) optical links are an attractive technology to meet the growing interconnect bandwidth demand in data center applications. This paper presents a multi-channel hybridintegrated photonic receiver based on microring drop filters and waveguide photodetectors implemented in a 130 nm SOI process and high-speed optical front-ends designed in 65 nm CMOS. The source-synchronous receiver utilizes an LC injection-locked oscillator (ILO) in the clock path for improved jitter filtering, while maintaining correlated jitter tracking with the data channels. Receiver sensitivity is improved with a large input-stage feedback resistor transimpedance amplifier (TIA) cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE). In order to stabilize the microring drop filter resonance wavelength, a peak-detector-based thermal tuning loop is implemented with a 0.7 nm range at 43 μW/GHz efficiency. When tested with a waveguide photodetector with 0.45 A/W responsivity, the receiver achieves -8.0 dBm OMA sensitivity at a BER = 10-12 with a jitter tolerance corner frequency near 20 MHz and a per-channel power consumption of 17 mW including amortized clocking power.

PAM4 silicon photonic microring resonator-based transceiver circuits

Increased data rates have motivated the investigation of advanced modulation schemes, such as four-level pulseamplitude modulation (PAM4), in optical interconnect systems in order to enable longer transmission distances and operation with reduced circuit bandwidth relative to non-return-to-zero (NRZ) modulation. Employing this modulation scheme in interconnect architectures based on high-Q silicon photonic microring resonator devices, which occupy small area and allow for inherent wavelength-division multiplexing (WDM), offers a promising solution to address the dramatic increase in datacenter and high-performance computing system I/O bandwidth demands. Two ring modulator device structures are proposed for PAM4 modulation, including a single phase shifter segment device driven with a multi-level PAM4 transmitter and a two-segment device driven by two simple NRZ (MSB/LSB) transmitters. Transmitter circuits which utilize segmented pulsed-cascode high swing output stages are presented for both device structures. Output stage segmentation is utilized in the single-segment device design for PAM4 voltage level control, while in the two-segment design it is used for both independent MSB/LSB voltage levels and impedance control for output eye skew compensation. The 65nm CMOS transmitters supply a 4.4Vppd output swing for 40Gb/s operation when driving depletion-mode microring modulators implemented in a 130nm SOI process, with the single- and two-segment designs achieving 3.04 and 4.38mW/Gb/s, respectively. A PAM4 optical receiver front-end is also described which employs a large input-stage feedback resistor transimpedance amplifier (TIA) cascaded with an adaptively-tuned continuous-time linear equalizer (CTLE) for improved sensitivity. Receiver linearity, critical in PAM4 systems, is achieved with a peak-detector-based automatic gain control (AGC) loop.