Ashutosh Kumar Singh

Candida haemulonii species complex: an emerging species in India and its genetic diversity assessed with multilocus sequence and amplified fragment-length polymorphism analyses.

Emerging Microbes and Infections (2016) 5, e49; doi:10.1038/emi.2016.49; published online 25 May 2016

Design and synthesis of reversible arithmetic and Logic Unit (ALU)

In low power circuit design, reversible computing has become one of the most efficient and prominent techniques in recent years. In this paper, reversible Arithmetic and Logic Unit (ALU) is designed to show its major implications on the Central Processing Unit (CPU).In this paper, two types of reversible ALU designs are proposed and verified using Altera Quartus II software. In the proposed designs, eight arithmetic and four logical operations are performed. In the proposed design 1, Peres Full Adder Gate (PFAG) is used in reversible ALU design and HNG gate is used as an adder logic circuit in the proposed ALU design 2. Both proposed designs are analysed and compared in terms of number of gates count, garbage output, quantum cost and propagation delay. The simulation results show that the proposed reversible ALU design 2 outperforms the proposed reversible ALU design 1 and conventional ALU design.

Modelling the XOR/XNOR Boolean Functions Complexity Using Neural Network

This paper propose a model for the complexity of Boolean functions with only XOR/XNOR min-terms using back propagation neural networks (BPNNs) applied to binary decision diagrams (BDDs). The developed BPNN model (BPNNM) is obtained through the training process of experimental data using Brain Maker software package. The outcome of this model is a unique matrix for the complexity estimation over a set of BDDs derived from randomly generated Boolean expressions with a given number of variables and XOR/XNOR min-terms. The comparison results of the experimental and back propagation neural networks mode (BPNNM) underline the efficiency of this approach, which is capable of providing some useful clues about the complexity of the final circuit implementation.

Multilayer perceptrons neural network based Web spam detection application

Web spam detection is a crucial task due to its devastation towards Web search engines and global cost of billion dollars annually. For these reasons, a multilayered perceptrons (MLP) neural network is presented in this paper to improve the Web spam detection accuracy. MLP neural network is used for Web spam classification due to its flexible structure and non-linearity transformation to accommodate latest Web spam patterns. An intensive investigation is carried out to obtain an optimal number of hidden neurons. Both Web spam link-based and content-based features are fed into MLP network for classification. Two benchmarking datasets - WEBSPAM-UK2006 and WEBSPAM-UK2007 are used to evaluate the performance of the proposed classifier. The overall performance is compared with the state of the art support vector machine (SVM) which is widely used to combat Web spam. The experiments have shown that MLP network outperforms SVM up to 14.02% on former dataset and up to 3.53% on later dataset.

Effect of Quine-McCluskey simplification on Boolean space complexity

The minimization of logic gates is needed to simplify the hardware design area of programmable logic arrays (PLAs) and to speed up the circuits. The VLSI designers can use minimization methods to produce high speed, inexpensive and energy-efficient integrated circuits with increased complexity. Quine-McCluskey (Q-M) is an attractive algorithm for simplifying Boolean expressions because it can handle any number of variables. This paper describes a new model for the estimation of circuit complexity, based on Quine-McCluskey simplification method. The proposed method utilizes data derived from Monte-Carlo simulations for any Boolean function with different count of variables and product term complexities. The model allows design feasibility and performance analysis prior to the circuit realization.

A Technique for Representing Multiple Output Binary Functions with Applications to Verification and Simulation

This paper presents a technique for representing multiple-output binary and word-level functions in GF(JV) (where N = pm, p is a prime number, and m is a nonzero positive integer) based on decision diagrams (DDs). The presented DD is canonical and can be made minimal with respect to a given variable order. The DD has been tested on benchmarks, including integer multiplier circuits, and the results show that it can produce better node compression (more than an order of magnitude in some cases) compared to shared binary DDs (BDDs). The benchmark results also reflect the effect of varying the input and output field sizes on the number of nodes. Methods of graph-based representation of characteristic and encoded characteristic functions in GF(iV) are also presented. Performance of the proposed representations has been studied in terms of average path lengths and the actual evaluation times with 50,000 randomly generated patterns on many benchmark circuits. All of these results reflect that the proposed technique can outperform existing techniques.

Link-based web spam detection using weight properties

Link spam is created with the intention of boosting one target’s rank in exchange of business profit. This unethical way of deceiving Web search engines is known as Web spam. Since then many anti-link spam detection techniques have constantly being proposed. Web spam detection is a crucial task due to its devastation towards Web search engines and global cost of billion dollars annually. In this paper, we proposed a novel technique by incorporating weight properties to enhance the Web spam detection algorithms. Weight properties can be defined as the influences of one Web node towards another Web node. We modified existing Web spam detection algorithms with our novel technique to evaluate the performances on a large public Web spam dataset – WEBSPAM-UK2007. The overall performance have shown that the modified algorithms outperform the benchmark algorithms up to 30.5 % improvement at host level and 6.11 % improvement at page level.

Low power high output impedance high bandwidth QFGMOS current mirror

Current mirror is a basic block of any mixed-signal circuit for example in an analog-to-digital converter. Its precise performance is the key requirement for analog circuits where offset is a measure issue. The key parameter which defines the performance of current mirror is its input/output impedance, input swing, and bandwidth. In this paper, a low power design of current mirror using quasi-floating gate MOS transistor is presented. The proposed current mirror boosts its output impedance in range of giga-ohm through use of regulated cascode structure followed by super-cascode. Another improvement is done in reduced input compliance voltage limits with the help of level shifter. The proposed current mirror operates well for input current range 0-700@mA with an input and output impedance of 160@W and 8.55G@W respectively and high bandwidth of 4.05GHz. The total power consumption of the proposed current mirror is about 0.84mW. The low power consumption with enhanced output impedance and bandwidth suits proposed current mirror for various high-speed analog designs. Performance of the presented current mirror circuit is verified using HSpice simulations on 0.18@mm mixed-mode twill-well technology at a supply voltage of +/-0.5V.

EFFICIENT METHODOLOGIES TO HANDLE HANGING PAGES USING VIRTUAL NODE

In this article we first explain the knowledge extraction (KE) process from the World Wide Web (WWW) using search engines. Then we explore the PageRank algorithm of Google search engine (a well-known link-based search engine) with its hidden Markov analysis. We also explore one of the problems of link-based ranking algorithms called hanging pages or dangling pages (pages without any forward links). The presence of these pages affects the ranking of Web pages. Some of the hanging pages may contain important information that cannot be neglected by the search engine during ranking. We propose methodologies to handle the hanging pages and compare the methodologies. We also introduce the TrustRank algorithm (an algorithm to handle the spamming problems in link-based search engines) and include it in our proposed methods so that our methods can combat Web spam. We implemented the PageRank algorithm and TrustRank algorithm and modified those algorithms to implement our proposed methodologies.

PyBot: An Algorithm for Web Crawling

PyBot is Web Crawler developed in Python to crawl the Web using Breadth First Search (BFS). The success of the World Wide Web (WWW), which itself built on the open internet, has changed the way how human share and exchange information and ideas. With the explosive growth of the dynamic Web, users have to spend much time just to retrieve a small portion of the information from the Web. The birth of the search engines have made human lives easier by simply taking them to the resources they want. Web crawler is a program used by search engines to retrieve information from the World Wide Web in an automated manner. Keywords− Crawler; Robots; Spiders; Robots Protocol; Crawler Policies