Ashutosh S. Dhodapkar

Comparing program phase detection techniques

Detecting program phase changes accurately is an important aspect of dynamically adaptable systems. Three dynamic program phase detection techniques are compared - using instruction working sets, basic block vectors (BBV), and conditional branch counts. Because program phases are difficult to define, we compare the techniques using a variety of metrics. BBV techniques perform better than the other techniques providing higher sensitivity and more stable phases. However, the instruction working set technique yields 30% longer phases than the BBV method, although there is less stability within phases. On average, the methods agree on phase changes 85% of the time. Of the 15% of time they disagree, the BBV method is more efficient at detecting performance changes. The conditional branch counter technique provides good sensitivity, but is less effective at detecting major phase changes. Nevertheless, the branch counter technique correlates 83% of the time with the BBV based technique. As an auxiliary result, we show that techniques based on procedure granularities do not perform as well as those based on instruction or basic block granularities. This is mainly due to their inability to detect changes within procedures.

TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator

We present TEM 2 P 2 EST, a flexible, cycle-accurate micro-architectural power/performance analysis tool based on SimpleScalar. The goal was to build a flexible simulation tool, incorporating several estimation models and providing a scalable framework for future development. This approach is based on the fact that different power models have different tradeoffs in terms of power estimation accuracy and flexibility/scalability. The simulator generates power estimates based on either empirical data or analytical models. In future, other modes like estimation based on RTL extraction can be included. The tool includes analytical models for dynamic and leakage power, di/dt power, dual V 1 support and process technology scaling options. It has a thermal model built to study thermal issues and techniques like clock throttling. Initial studies show that our results are consistent and match well with real design simulated with SPICE. In addition, we validated our temperature model with measurement on a typical microprocessor heat solution.

Timing reconfigurable microarchitectures for power efficiency

Summary form only given. Modern microprocessors are designed with a fixed set of microarchitected resources. On the other hand, program resource requirements are known to vary across programs and even within a program as it goes through different phases of execution. This mismatch between the design and program requirements often leads to suboptimal power and/or performance. We present an adaptive microarchitecture that tailors itself dynamically to match changing program requirements. The goal of adaptation in this work is to achieve power efficiency without suffering significant performance degradation. The microarchitecture employs four multiconfiguration units nstruction cache, data cache, unified L2 cache and branch predictor along with light weight profiling hardware and sophisticated tuning algorithms. The profiling hardware collects working set signatures using a simple hash function and sparse sampling in order to reduce profiling hardware complexity. The tuning algorithms use these signatures to accurately detect program phase changes and decouple the tuning of each unit using a novel technique. Detailed simulations show that the best performing algorithm achieves subthreshold leakage power reductions as high as 76% for instruction cache, 46% for data cache, 63% for L2 cache and 73% for the branch predictor in the benchmarks studied. On average, the algorithm leads to 1.1% performance degradation while achieving 44%, 17%, 19%, and 28% reduction in subthreshold leakage power for instruction cache, data cache, L2 cache and branch predictor, respectively.

INTEGRATED PERFORMANCE, POWER, AND THERMAL MODELING

In current microprocessor designs, power dissipation has become a first class design constraint alongside performance and total chip cost. In order to design power efficient microprocessors, it is essential for architects to estimate the power/energy consumption and study thermal effects early on in the design process. This paper describes a method that can be used to study power/performance tradeoffs during the microarchitecture definition phase. The modeling and simulation methods provide an integrated framework for evaluating the effects of microarchitectural parameters on performance, power and thermal behavior. The method also provides a flexible interface for supporting several power and thermal models of varying degrees of detail. The paper introduces a tool based on this method that can be used to systematically study new architectures, designs and optimize them for power and/or performance. The tool also has a flexible interface which is to be easily extended for future power/performance analysis and optimization techniques.

Tuning adaptive microarchitectures

Microprocessors are designed with a fixed set of microarchitectural resources. However, resource requirements vary across programs and within a program as it passes through different phases of execution. This mismatch between the microarchitecture and program requirements leads to sub-optimal power/performance. We present an adaptive microarchitecture that dynamically adapts to changing program requirements in order to achieve power efficiency with minimal performance loss. The microarchitecture employs four multi-configuration units which are controlled by a phase-based tuning algorithm. We show, via simulation, that the best performing tuning algorithm achieves significant reduction in leakage power with performance loss of ~1%.