George Cai

TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator

We present TEM 2 P 2 EST, a flexible, cycle-accurate micro-architectural power/performance analysis tool based on SimpleScalar. The goal was to build a flexible simulation tool, incorporating several estimation models and providing a scalable framework for future development. This approach is based on the fact that different power models have different tradeoffs in terms of power estimation accuracy and flexibility/scalability. The simulator generates power estimates based on either empirical data or analytical models. In future, other modes like estimation based on RTL extraction can be included. The tool includes analytical models for dynamic and leakage power, di/dt power, dual V 1 support and process technology scaling options. It has a thermal model built to study thermal issues and techniques like clock throttling. Initial studies show that our results are consistent and match well with real design simulated with SPICE. In addition, we validated our temperature model with measurement on a typical microprocessor heat solution.

Power-sensitive multithreaded architecture

The power consumption of microprocessors is becoming increasingly important in design decisions, not only in mobile processors, but also now in high-performance processors. Power-conscious design must therefore go beyond technology and low-level design, but also change the way modern processors are architected. A multithreading processor is attractive in the context of low-power or power-constrained devices for many of the same reasons that enable its high throughput. Primarily, it supplies extra parallelism via multiple threads, allowing the processor to rely much less heavily on speculation. We show that a simultaneous multithreading processor utilizes up to 22% less energy per instruction than a single-threaded architecture. We also explore other power optimizations that are particular to multithreaded architectures, either because they are unavailable to or unreasonable for single-thread architectures.

Support for High-Frequency Streaming in CMPs

As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed high-latency memory subsystems and ever-increasing wire delays, require parallelization techniques to create partially or fully independent threads to improve performance. Unfortunately, developers and compilers alike often fail to find sufficient independent work of this kind. Recently proposed pipelined streaming techniques have shown significant promise for both manual and automatic parallelization. These techniques have wide-scale applicability because they embrace inter-thread dependences (albeit acyclic dependences) and tolerate long-latency communication of these dependences. This paper addresses the lack of architectural support for this type of concurrency, which has blocked its adoption and hindered related language and compiler research. We observe that both manual and automatic techniques create high-frequency streaming threads, with communication occurring every 5 to 20 instructions. Even while easily tolerating inter-thread transit delays, high-frequency communication makes thread performance very sensitive to intra-thread delays from the repeated execution of the communication operations. Using this observation, we define the design-space and evaluate several mechanisms to find a better trade-off between performance and operating system, hardware, and design costs. From this, we find a light-weight streaming-aware enhancement to conventional memory subsystems that doubles the speed of these codes and is within 2% of the best-performing, but heavy-weight, hardware solution

INTEGRATED PERFORMANCE, POWER, AND THERMAL MODELING

In current microprocessor designs, power dissipation has become a first class design constraint alongside performance and total chip cost. In order to design power efficient microprocessors, it is essential for architects to estimate the power/energy consumption and study thermal effects early on in the design process. This paper describes a method that can be used to study power/performance tradeoffs during the microarchitecture definition phase. The modeling and simulation methods provide an integrated framework for evaluating the effects of microarchitectural parameters on performance, power and thermal behavior. The method also provides a flexible interface for supporting several power and thermal models of varying degrees of detail. The paper introduces a tool based on this method that can be used to systematically study new architectures, designs and optimize them for power and/or performance. The tool also has a flexible interface which is to be easily extended for future power/performance analysis and optimization techniques.

Retrospective on “Power-Sensitive Multithreaded Architecture”

This article provides a retrospective look at the research that went into the 2000 ICCD paper “Power-Sensitive Multithreaded Architecture”. At the time, simultaneous multithreading processors were soon to be commercially available and power consumption was proving to be a challenging design constraint. That research introduced optimizations that increased power and energy efficiency through multithreading, while maintaining performance. This article discusses the optimizations in the paper and discusses how processor designs have changed since its publication.