Atanu Chattopadhyay

GALDS: a complete framework for designing multiclock ASICs and SoCs

A Globally Asynchronous, Locally Synchronous (GALS) system with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimal power consumption. With the mechanism for implementing dynamic voltage scaling at each synchronous domain left up to the designer, our Globally Asynchronous, Locally Dynamic System (GALDS) provides a top-down, system-level means to maximize power reduction in an integrated circuit and facilitate system-on-a-chip (SoC) design. Our solution includes three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently clocked synchronous blocks , an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally controlled oscillator to generate the global fixed frequency clocks required by the all-digital dynamic clock generator. In addition to being capable of reducing power consumption when combined with dynamic voltage scaling, a GALDS design benefits from numerous other advantages such as simplified clock distribution, high performance operation and faster time-to-market through the modular nature of the architecture.

Reference-Based Clock Distribution Architectures

This paper examines the use of clock distribution architectures employing a reference-based skew compensation technique. For each clock domain, a bi-directional clock line is daisy-chained using specially designed switches at each tap in the distribution. Daisy-chaining the clock decreases the clock load by eliminating the redundant paths used to equalize delays in traditional H-tree distributions. Clock skew is accounted for by actively synchronizing each local clock to a position directly between forward and reverse-moving reference clocks. This reference-based clocking strategy achieves a set of skew-tolerant clocks at each tap in a daisy-chain. The design provides simple-to-layout and scalable multipoint skew compensation useful for large designs. The implementation of a reference-based clocking chain is outlined, followed by the description of single clock and multi-clock architectures using this design strategy.

Expandable and robust laboratory for microprocessor systems

We present the design and use of the McGumps laboratory kit for teaching microprocessor and embedded systems. The kit facilitates efficient learning of relevant hardware and software design techniques that will not get outdated soon. We describe the typical use of this kit in our courses.

Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks

We present a clock distribution network that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modular, standard cell-based design approach that mitigates the effect of intra-die temperature and process variances. We route the clock line serially, using an averaging technique to eliminate skew between clock regions in a domain. Routing clock lines serially allows optimal wire usage for clock networks by eliminating the redundant wires required to match path delays. Our clock network provides control over regional clock skews, can be used in beneficial skew applications and facilitates silicon-debug. Serial clocking permits the use of routing switches in the clock network and allows post-silicon resizing and reshaping of clock domains. Defective sections of the clock network can be bypassed, providing post silicon repair capability. The system uses a closed-loop synchronization phase to combine the clock skew reduction of an actively synchronized clock network with an open-loop operating phase that minimizes power consumption like passive clock networks. Our clock network provides significant flexibility for application-specific integrated circuit, system-on-chip, and field-programmable gate-array designs, exhibiting good operating characteristics everywhere in the design envelope. Our silicon implementation achieves a maximum edge-to-edge uncertainty of 80 ps for regional clocks, which is roughly equal to the cycle-to-cycle jitter of the on-chip clock source.

Reconfigurable Clock Distribution Circuitry

We present the circuitry required for implementing a multi-clock reconfigurable, reprogrammable clock distribution network for integrated circuits using a reference-based scheme for skew compensation. In the scheme, a device is subdivided into multiple regions and a bi-directional clock distribution line is daisy-chained through the device, connecting each region in the domain. Switching structures that can be used to re-route the clock chain are added where needed. The proposed design simplifies layout for irregularly shaped clock domains and provides flexibility to designers by enabling post-fabrication changes to the clock distribution network. Reconfigurable clock distribution networks can be used in some ASICs, SoCs and FPGAs. The reference-based approach used is applicable to both single and multiple clock distributions

High speed asynchronous structures for inter-clock domain communication

This paper describes a globally asynchronous, locally dynamic system (GALDS) design paradigm. In a GALDS design, many synchronous blocks are inter-connected using dedicated asynchronous links. Each synchronous block is associated with a local clock generator and features dynamic frequency scaling in order to utilize the least possible power for the required performance to be achieved. Two different asynchronous structures are explored in this paper and they each feature high throughput, modular design and high tolerance to metastability errors that occur when communicating between clock domains. These structures utilize a 4-phase dual track asynchronous control circuit to control either a single direction FIFO with data traveling uniquely in one direction or a bidirectional FIFO that is capable of transmitting data simultaneously in both directions by precisely controlling when data has access to a common, shared datapath. These structures have been created in TSMCs CMOSP18 technology.

Design and operating characteristics of a reconfigurable clock distribution network

In this paper, we provide an overview of our reprogrammable multi-clock distribution scheme. We present potential architectures using this scheme, information on controller requirements and the systems operating characteristics, including a skew and jitter study. We show that reference-based clocking provides a skew tolerant scalable solution that can re-route clocks using specially designed switch-points, post-silicon. Our clock distribution is able to combine the best aspects of both active and passive clock distribution architectures by using distinct synchronization and operation phases. We show through simulation that our system is resilient enough to temperature and voltage fluctuations to be used in an ASIC, SoC or FPGA environment.

A globally asynchronous locally dynamic system for ASICs and SoCs

An architecture that combines a Globally Asynchronous, Locally Synchronous (GALS) [1,2] design style with dynamic voltage and frequency scaling can use the slowest frequency possible to accomplish a task with minimum power consumption. The proposed Globally Asynchronous, Locally Dynamic System (GALDS) requires three distinct components: a novel bidirectional asynchronous FIFO to communicate between independently-clocked synchronous blocks [3], an all-digital dynamic clock generator to quickly and glitchlessly switch between frequencies and a digitally-controlled oscillator to generate global fixed frequency clocks required by the all-digital dynamic clock generator. These circuits have been designed and simulated for all the tasks required to implement a complete GALDS infrastructure. The architecture is easily scaled due to the modular nature of these circuits and is useful for a wide range of applications.

Serial reconfigurable mismatch-tolerant clock distribution

We present an unconventional clock distribution that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modular standard cell approach that compensates intra-die temperature and process variances. Our clock distribution provides control over regional clock skew, permits use in benbeneficial skew applications and facilitates silicon-debug. By addingeficial skew applications and facilitates silicon-debug. By adding routing to the serial clock network, we permit post-silicon resizing and reshaping of clock domains. Defective sections of the clock network can be bypassed, providing post silicon repair capability to the network.

Built-in clock skew system for on-line debug and repair

We present a low-cost on-line system for clock skew management in integrated circuits. Our built-in clock skew system (BICSS) uses a centralized approach to identify, quantify and correct skew using a two-step method. The technique assesses the time-off-light between the central debug circuitry and each region, or tap under test to account for the measurement error due to differences in path length common in existing techniques. The system can be used to detect skew above a user-adjustable margin using a variable tolerance phase detector. The result is a solution which provides silicon debug and repair capability of on-chip clock skews with a very small area overhead.