Zeljko Zilic

Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis

Assertion based design, and more specifically, assertion based verification (ABV) is quickly gaining wide acceptance in the design community. Assertions are mainly targeted at functional verification during the design and verification phases. In this paper, we concentrate on the use of assertions in post-fabrication silicon debug. We develop tools that efficiently generate the checkers from assertions, for their inclusion in the debug phase. We also detail how a checker generator can be used as a means of circuit design for certain portions of self test circuits, and more generally the design of monitoring circuits. Efficient subset partitioning of checkers for a dedicated fixed-size reprogrammable logic area is developed for efficient use of dedicated debug hardware

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing

A popular network topology for network-on-chip (NoC) implementations is the two-dimensional mesh. A disadvantage of the mesh topology is in its large communication radius. By partitioning a two-dimensional mesh into several sub-meshes and connecting them using a global interconnect, we can reduce the average number of hops for global traffic. This paper presents a hybrid architecture that partitions a large 2D-mesh into several smaller sub-meshes which are globally connected using a hierarchical ring interconnect. Hierarchical rings have been selected for study because of their simplicity, speed and efficiency in embedding onto a circuit layout, as well as for their suitability for efficient cache coherent protocols. An original SystemC modeling platform was implemented in order to compare the traditional 2D-mesh with the hybrid ring architectures and the simulation results will show that our hybrid architecture does indeed have a positive effect on the average hop count

Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug

This paper presents techniques that enhance automatically generated hardware assertion checkers to facilitate debugging within the assertion-based verification paradigm. Starting with techniques based on dependency graphs, we construct the algorithms for counting and monitoring the activity of checkers, monitoring assertion completion, as well as introduce the concept of assertion threading. These debugging enhancements offer increased traceability and observability within assertion checkers, as well as the improved metrics relating to the coverage of assertion checkers. The proposed techniques have been successfully incorporated into the MBAC checker generator.

Automata-based assertion-checker synthesis of PSL properties

Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We present a technique for automata-based checker generation of PSL properties for dynamic verification. A full automata-based approach allows an entire assertion to be represented by a single automaton, hence allowing optimizations which can not be done in a modular approach where sub-circuits are created only for individual operators. For this purpose, automata algorithms are developed for the base cases, and a complete set of rewrite rules is developed and applied for all other operators. We show that the generated checkers are resource-efficient for use in hardware emulation, simulation acceleration and silicon debug

Incorporating efficient assertion checkers into hardware emulation

Assertion-based verification (ABV) is emerging as a paramount technique for industrial-strength hardware verification, especially through the emerging property specification language (PSL). Since PSL introduces significant overhead to simulators, in this paper we present the infrastructure for hardware emulation capable of supporting ABV. We develop a tool that generates hardware assertion checkers for inclusion into efficient circuit emulation. The MBAC checker generator is outlined, together with the algorithms for optimized assertion-circuit generation. Experiments show that MBAC outperforms the best known checker-generator.

Echo cancellation in IP networks

Voice transmission over IP networks imposes new DSP challenges. Package loss and latency caused by packet buffering have the fundamental influence on the speech quality. These features have also an impact on the line echo canceller (EC) performance. The constant latency greater than 60 milliseconds usually causes that an echo is very well audible even for a short echo path delay. Therefore, the EC must be deployed on each 2-wire/4-wire connection while on a conventional transmission only toll connections require EC. Such a large total delay requires short convergence time and sufficient Echo Return Loss Enhancement (ERLE). Further, package loss that is related to non-stationary intervals of speech imposes stringent requirements on EC performance in tracking statistical variations of the signal. Overally, IP telephony requires more robust and less expensive EC than conventional networks. In this paper we address the basic design issues in the EC for IP telephony. We show that classical Least Mean Square (LMS) algorithms are rather inappropriate and offer an alternative solution.

Reliability aware NoC router architecture using input channel buffer sharing

To address the increasing demand for reliability in on-chip networks, we proposed a novel Reliability Aware Virtual channel (RAVC) NoC router micro-architecture that enables both dynamic virtual channel allocations and the rational sharing among the buffers of different input channels. In particular, in the case of failure in routers, the virtual channels of routers surrounding the faulty routers can be totally recaptured and reassigned to other input ports. Moreover, our proposed RAVC router isolates the faulty router from occupying network bandwidth. Experimental result shows that proposed micro-architecture provides 7.1% and 3.1 % average latency decrease under uniform and transpose traffic pattern. Considering the existence of failures in routers of on-chip network, RAVC provides 28% and 16% decrease in the average packet latency under the uniform and transpose traffic pattern respectively.

Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties

Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We present a technique for automata-based checker generation of PSL properties for dynamic verification. A full automata-based approach allows an entire assertionu to be represented by a single automaton, hence allowing optimizations which can not be done in a modular approach where sub-circuits are created only for individual operators. For this purpose, automata algorithms are developed for the base cases, and a complete set of rewrite rules is developed and applied for all other operators. We show that the generated checkers anre resource-efficient for use in hardwarre emulation, simulation acceleration and silicon debug.

Dynamic clock management for low power applications in FPGAs

Low power techniques employing dynamically controlled clock rates offer potentially powerful energy saving capabilities. In this paper, we consider the application of this low power technique to FPGAs, where we reduce energy waste in clock distributions. We show that current FPGA clock managers are inadequate for use in dynamically controlled systems. We provide an architectural block, the dynamic clock divider, that can be added either internally to clock managers or as user logic, to allow dynamic clock management.

Architectures of increased availability wireless sensor network nodes

Wireless sensor networks (WSNs) are being increasingly used in applications where low energy consumption and low cost are the overriding considerations. With increased use, their reliability, availability and serviceability need to be addressed from the outset. Conventional schemes of adding redundant nodes and incorporating reliability in control protocols can effectively improve only the reliability of the overall WSN. The availability and serviceability of WSN nodes can be addressed by providing the remote testing and repair infrastructure for the individual sensor nodes that is well matched with existing on-board test infrastructure, including standard JTAG chains. We propose and evaluate scalable architectures of WSN nodes for increased availability as well as implement the proposed solutions using COTS components.