Atif Raza Jafri

ASIP-Based Universal Demapper for Multiwireless Standards

The emergence of diverse wireless standards, employed in various transmission environments, is leading towards evolution of flexible radio platforms. In this letter, we are presenting the first universal Application Specific Instruction-set Processor (ASIP)-based flexible demapper component of a radio platform. The proposed architecture provides full flexibility ranging from low complexity QPSK Gray-mapped constellations to high complexity 256-QAM rotated constellations in turbo demodulation framework. The presented architecture provides the liberty to use this demapper both in iterative and noniterative receivers. Besides flexibility, ASIP synthesis results demonstrate a throughput of 606 Mega LLR per second for 16-QAM Gray-mapped constellation.

Exploring parallel processing levels in turbo demodulation

Iterative processing in a wireless base-band receiver ensures promising error rate performance at the cost of high processing time for data retrieval. Exploration of parallelism in iterative processes, while maintaining the error rate performance, contributes toward fulfilling the high transmission rate requirements of emerging wireless communication standards. In this paper, parallelism levels available in the constituent components of turbo demodulation system have been classified. To compare the parallel execution performance to a serial, results of a high speed parallel turbo demodulation software model are presented. For a highly parallel turbo demodulation system, comprised of 16 demappers and 32 decoders running concurrently, the throughput can be enhanced 27 times as compared to a serial architecture for 16-QAM modulation. Parallelism efficiency is also tabulated for 16-QAM and 256-QAM, with different architectural configurations which can benefit the hardware designer about architectural efficiency to attain high throughput.

Towards an Optimized Architecture for Unified Binary Huff Curves

Applying unified formula while computing point addition and doubling provides immunity to Elliptic Curve Cryptography (ECC) against power analysis attacks (a type of side channel attack). One of the popular techniques providing this unifiedness is the Binary Huff Curves (BHC) which got attention in 2011. In this paper we are presenting highly optimized architectures to implement point multiplication (PM) on the standard NIST curves over GF(2163) and GF(2233) using BHC. To achieve a high throughput over area ratio, first of all, we have used a simplified arithmetic and logic unit. Secondly, we have reduced the time to compute PM through Double and Add algorithm. This is achieved by increasing the frequency of operation through a 2-stage pipelined architecture. The increase in clock cycles caused by consequent pipeline hazards is controlled through optimal scheduling of computations involved in PM. The synthesis results show that our designs can work up to a frequency of 377MHz on Xilinx Virtex 7 FPGA. Moreover, the overall throughput/area ratio achieved through the adopted approach is up to 20% higher while comparing with available state-of-the-art solutions.

A new ultralightweight RFID mutual authentication protocol: SASI using recursive hash

RFID is one of the most prominent identification schemes in the field of pervasive systems. Nonline of sight capability makes RFID systems much better choice than its contended systems (such as barcode, magnetic tape, etc.). Since the RFID uses wireless channel for communication with its associated devices, there should be some optimal encryption methods to secure the communicating data from adversaries. Several researchers have proposed ultralightweight mutual authentication protocols (UMAPs) to secure the RFID systems in cost effective manner. Unfortunately most of the previously proposed UMAPs are later found to be vulnerable against various desynchronization, Denial of Service (DoS), traceability, and full disclosure attacks. In this paper, we present a more sophisticated UMAP to provide Strong Authentication and Strong Integrity (SASI) using recursive hash function. The proposed protocol incorporates only simple bitwise logical operators XOR, Rot, and nontriangular function (recursive hash) in its design, which can be efficiently implemented with a low cost passive RFID tag. The performance analysis of the protocol proves the conformation of the proposed protocol with EPC-C1G2 passive tags. In addition to privacy and security, small chip area (miniaturization) is another design constraint (which is mandatory requirement for a protocol to be considered as ultralightweight authentication protocol). We have also proposed and implemented the efficient hardware design of the proposed protocol for EPC-C1G2 tags. Both the FPGA and ASIC implementation flows have been adopted. The FPGA flow is primarily used to validate the functionality of the proposed hardware design whereas ASIC flow (using TSMC 0.35 μm library) is used to validate the gate count. To the best of our knowledge, this is the first FPGA and ASIC implementation of any ultralightweight RFID authentication protocol.

Parallel MIMO Turbo Equalization

Although the use of filter based equalizer with Multi Input Multi Output (MIMO) turbo equalization ensures promising error rate performance at low area overhead, it adds to the latency already imposed by turbo decoding. In this letter, in order to address the ever increasing requirements of high throughput and low latency, two parallelism techniques are proposed and analyzed for MIMO turbo equalization. Results demonstrate that significant speed gain and parallelism efficiency can be attained for different MIMO Spatial Multiplexing (SM) configurations without degrading the error rate performance.

Rapid design and prototyping of universal soft demapper

Rapid advancements in wireless communication standardization is leading toward the evolution of flexible radio platforms. At the same time, the resulting severe time-to-market constraints make inevitably resorting to new design methodologies to shorten the development cycle. In this paper we are presenting the steps involved in rapid design, validation, and prototyping of the first multi standard ASIP-based universal demapper. The presented ASIP provides flexibility to support any modulation type using up to 8 bits per symbol both in turbo and non-turbo context. The rapid development flow has been described starting from ASIP modeling in LISA ADL till the FPGA implementation. Using a logic emulation board integrating Virtex 5 LX330 FPGA, the prototype achieves a throughput of 102 Mega LLR/sec for Gray mapped 16-QAM constellation at a clock frequency of 156 MHz. The highly reduced size of the ASIP, comprising of 1596 (0.7%) slice registers, 2627 (1.2%) slice LUTs and 6 DSP48Es, enables the user to achieve even higher throughputs by using multi-ASIP architecture.

Heterogeneous Multi-ASIP and NoC-Based Architecture for Adaptive Parallel TBICM-ID-SSD

A novel multi-ASIP and network-on-chip (NoC) based flexible architecture for parallel iterative demapping with turbo decoding using signal space diversity (TBICM-ID-SSD) is presented in this brief. The proposed heterogeneous multi-ASIP architecture uses multiple instances of two types of application-specific instruction-set processor (ASIP): one dedicated for turbo decoding and the second for demodulation, besides butterfly-topology-based NoCs. This architecture presents novel and outstanding levels of flexibility and scalability in the design of advanced iterative receivers. It supports modulation schemes from BPSK to 256-QAM for any mapping style and supports 8 state single and double binary turbo codes used in 3GPP-LTE, DVB-RCS, and WiMAX. FPGA prototyping results are presented, and the extra hardware cost required to enable turbo demodulation is evaluated.

Comparative analysis of flexible cryptographic implementations

Flexible hardware implementations of cryptographic algorithms in the real time applications have been frequently proposed. This paper classifies the state-of-the-art research practices through a Systematic Literature Review (SLR) process. The selected researches have been classified into three design categories: crypto processor, crypto coprocessor and multicore crypto processor. Subsequently, comparative analysis in terms of flexibility, throughput and area is presented. It facilitates the researchers and designers of the domain to select an appropriate design approach for a particular algorithm and/or application.

Hardware Complexity Reduction in Universal Filtered Multicarrier Transmitter Implementation

The inclusion of machine-type communication in the 5G technology has motivated the research community to explore new derivative waveforms of orthogonal frequency division multiplexing. Filter bank multicarrier, universal filtered multicarrier (UFMC), and generalized frequency division multiplexing techniques are under evaluation with respect to their suitability to 5G requirements. In addition to acceptable spectral performance, investigation on computational complexity reduction while addressing flexibility can help in the selection of suitable waveform among multiple options available for 5G. In this regard, based on analysis of computation involved in UFMC waveform construction, few reduced complexity solution for UFMC transmitter implementations are recently proposed. However, hardware-implementation-related issues have not been discussed in detail. In this paper, we have proposed reduced complexity hardware solutions for all three constituent blocks, i.e., inverse discrete Fourier transform (IDFT), finite impulse response (FIR) filter, and spectrum shifting blocks of a UFMC transmitter. For IDFT part, a reduced complexity IFFT solution using Radix-2 decimation in a time technique is presented, where more than 42% computations can be avoided. It is also shown that how five times less number of multipliers can be used in an FIR filter to simplify filter architecture. Finally, a highly efficient method is presented to compute spectrum shifting coefficients through small sized lookup table.

Efficient Hardware Implementation of Ultralightweight RFID Mutual Authentication Protocol

Security and privacy are the two major concerns of radio-frequency identification (RFID) based identification systems. Several researchers have proposed ultralightweight mutual authentication protocols (UMAPs) to ensure the security of the low cost RFID tags in recent years. However, almost all of the previously proposed protocols have some serious security flaws and are vulnerable to various security attacks (full disclosure attack, desynchronization attack, impersonation attack, etc.). Recently, a more sophisticated and robust UMAP: Robust confidentiality integrity and authentication (RCIA)1 [U. Mujahid, M. Najam-ul-Islam and M. Ali Shami, RCIA: A new ultralightweight RFID authentication protocol using recursive hash, Int. J. Distrib. Sens. Netw. 2015 (2015) 642180] has been proposed. A new ultralightweight primitive, “recursive hash” has been used extensively in the protocol design which provides hamming weight unpredictability and irreversibility to ensure optimal security. In addition to security and...