Atsushi Kameyama

The design and implementation of a first-generation CELL processor

A CELL processor is a multi-core chip consisting of a 64b power architecture processor, multiple streaming processors, a flexible IO interface, and a memory interface controller. This SoC is implemented in 90nm SOI technology. The chip is designed with a high degree of modularity and reuse to maximize the custom circuit content and achieve a high-frequency clock-rate.

A novel resonant-type GaAs SPDT switch IC with low distortion characteristics for 1.9 GHz personal handy-phone system

A GaAs SPDT switch IC operating at a low power supply voltage of 2.7 V has been developed for use in Personal Handy-Phone System in the 1.9 GHz band. In combination with MESFETs with low on-resistance and high breakdown voltage, the resonant-type switch IC utilizes stacked FETs and an additional shunt capacitor at the receiver side in order to realize low insertion loss, high isolation and low distortion characteristics. An insertion loss of 0.55 dB and an isolation of 35.8 dB were obtained at 1.9 GHz. The IC also achieved a second order distortion of -54.3 dBc and an adjacent channel leakage power of -66 dBc at 600 kHz apart from 1.9 GHz at 19 dBm output power.

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

This paper reviews the design challenges that current and future processors must face, with stringent power limits and high frequency targets, and the design methods required to overcome the above challenges and address the continuing Giga-scale system integration trend. This paper then describes the details behind the design methodology that was used to successfully implement a first-generation CELL processor - a multi-core SoC. Key features of this methodology are broad optimization with fast rule-based analysis engines using macro-level abstraction for constraints propagation up/down the design hierarchy, coupled with accurate transistor level simulation for detailed analysis. The methodology fostered the modular design concept that is inherent to the CELL architecture, enabling a high frequency design by maximizing custom circuit content through re-use, and balanced power, frequency, and die size targets through global convergence capabilities. The design has roughly 241 million transistors implemented in 90 nm SOI technology with 8 levels of copper interconnects and one local interconnect layer. The chip has been tested at various temperatures, voltages, and frequencies. Correct operation has been observed in the lab on first pass silicon at frequencies well over 4GHz.

The design methodology and implementation of a first-generation CELL processor: a multi-core SoC

This paper reviews the design challenges that current and future processors must face with stringent power limits and high frequency targets, and the design methods required to address the continuing system integration trends. This paper then describes the implementation of a first-generation CELL processor and the design methods used to overcome the above challenges. A CELL processor consists of a 64 bit power architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multicore SoC, implemented in 90nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.

A 0.5-V power-supply scheme for low-power system LSIs using multi-V/sub th/ SOI CMOS technology

This paper proposes a novel power-supply scheme suitable for 0.5-V operating silicon-on-insulator (SOI) CMOS circuits. The system contains an on-chip buck DC-DC converter with over 90% efficiency, 0.5-V operating logic circuits, 100-MHz operating flip-flops at 0.5-V power supply, and level converters for the interface between the 0.5-V operating circuit and on-chip digital-to-analog (D/A) converters or external equipment. Based on the theory, the values of on-resistance and threshold voltage of SOI transistors are clarified for the 0.5-V/10-mW output DC-DC converter, which satisfies both high efficiency and low standby power. The proposed flip-flop can hold the data during the sleep with the use of the external power supply, while maintaining high performance during the active. The level converter comprises dual-rail charge transfer gates and a CMOS buffer with a cross-coupled nMOS amplifier to operate with high speed even in a conversion gain of higher than 6, where the conversion gain is defined as the ratio of the output and input signal swings. The test chip was fabricated for the 0.5-V power supply scheme by using multi-V/sub th/ SOI CMOS technology. The experimental results showed that the buck DC-DC converter achieved a conversion efficiency of 91% at 0.5-V/10-mW output with stable recovery characteristics from the sleep, and that the dual-rail level converter operated with a maximum data rate of 300 Mb/s with the input signal swing of 0.5 V.

High efficiency, low adjacent channel leakage 2-V operation GaAs power MESFET amplifier for 1.9-GHz digital cordless phone system

A low-voltage GaAs power amplifier for 1.9-GHz digital mobile communication applications such as PHS handsets has been developed, using refractory WNx/W self-aligned gate MESFETs with p-pocket layers. This power amplifier operates with a single low 2-V supply, and an output power of 21.0 dBm, a power gain of 22.3 dB, a low dissipated current of 162.9 mA and a high power-added efficiency of 38.5% were attained with a low 600-kHz adjacent channel leakage power of -58.0 dBc for 1.9-GHz /spl pi//4-shifted QPSK modulated input.

A new reduced clock-swing flip-flop: NAND-type keeper flip-flop (NDKFF)

A new reduced clock-swing flip-flop, named NAND-type Keeper Flip-Flop (NDKFF) is proposed. Compared with other conventional reduced clock-swing flip-flops such as HSFF and RCSFF, NDKFF features a simple configuration, which does not have additional clock drivers or does not have additional nand/or p-wells. Compared with the hybrid-latch flip-flop, 52% of the flip-flop power and 64% of the clocking power are saved in the case of 0.25 /spl mu/m CMOS technology. Moreover CLK-to-Q delay is comparable to that of conventional C2MOS-type master-slave flip-flop.

A symmetric GaAs MESFET structure with a lightly doped deep drain for linear amplifiers operating with a single low-voltage supply

An improved symmetric GaAs MESFET structure with a lightly doped deep source/drain is proposed for application to power amplifiers in mobile communication terminals. With lightly doped deep drain, the impact ionization falls as the electron current expands and the current density decreases. Thus, the breakdown voltage rises, while a high transconductance and low parasitic resistance are maintained. Furthermore, the symmetric structure suits for mass production because of its fabrication process without mask alignment precision. This structure was fabricated using the WNx/W self-aligned gate process, and DC and RF characteristics were evaluated. The power-added efficiency was 37% at an adjacent channel leakage power of -55 dBc for 37%-shift QPSK modulated input signals at 1.9 GHz with a single positive supply voltage of 3 V. The efficiency was also high at a lower supply voltage: 34% at 1.2 V.

A 6 K-gate GaAs gate array with a new large-noise-margin SLCF circuit

A 6 K-gate GaAs gate array has been successfully designed and fabricated using a novel large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN/SUB x/ gate selfaligned lightly doped drain (LDD) structure GaAs MESFET process. Chip size was 8.0/spl times/8.0 mm/SUP 2/. A basic cell can be programmed as an SLCF inverter, a two-input NOR, or a two-input NAND gate. The unloaded propagation delay time was 76 ps/gate a 1.2-mW/gate power dissipation. The increases in delay time due to various loading capacitances were 10 ps/fan-in, 45 ps/fan-out, and 0.64 ps/IF. A 16-b serial-to-parallel-to-serial (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation frequency of 852 MHz was achieved at a 952-mW power dissipation, including I/O buffers.

Single low voltage supply operation GaAs power MESFET amplifier with low-distortion gain-variable attenuator for 1.9-GHz personal handy phone systems

A GaAs power amplifier with a low-distortion, 10-dB gain attenuator has been developed for 1.9-GHz personal handy phone system (PHS). Single low 2.4-V supply operation was achieved by using power MESFETs with p-pocket layers. Furthermore, on account of an attenuator with cascaded shunt FET structure, very low 600-kHz adjacent channel leakage power (ACP) with sufficient, constant output power was attained regardless of any controlled gain. An output power of 21.1 dBm, a low dissipated current of 157 mA and a high power-added efficiency of 37.2% were obtained with ACP of -55 dBc.