D. Pham

The design and implementation of a first-generation CELL processor

A CELL processor is a multi-core chip consisting of a 64b power architecture processor, multiple streaming processors, a flexible IO interface, and a memory interface controller. This SoC is implemented in 90nm SOI technology. The chip is designed with a high degree of modularity and reuse to maximize the custom circuit content and achieve a high-frequency clock-rate.

A 2.2 W, 80 MHz superscalar RISC microprocessor

A 28 mW/MHz at 80 MHz structured-custom RISC microprocessor design is described. This 32-b implementation of the PowerPC architecture is fabricated in a 3.3 V, 0.5 /spl mu/m, 4-level metal CMOS technology, resulting in 1.6 million transistors in a 7.4 mm by 11.5 mm chip size. Dual 8-kilobyte instruction and data caches coupled to a high performance 32/64-b system bus and separate execution units (float, integer, loadstore, and system units) result in peak instruction rates of three instructions per clock cycle. Low-power design techniques are used throughout the entire design, including dynamically powered down execution units. Typical power dissipation is kept under 2.2 W at 80 MHz. Three distinct levels of software-programmable, static, low-power operation-for system power management are offered, resulting in standby power dissipation from 2 mW to 350 mW. CPU to bus clock ratios of 1/spl times/, 2/spl times/, 3/spl times/, and 4/spl times/ are implemented to allow control of system power while maintaining processor performance. As a result, workstation level performance is packed into a low-power, low-cost design ideal for notebooks and desktop computers. >

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor

This paper reviews the design challenges that current and future processors must face, with stringent power limits and high frequency targets, and the design methods required to overcome the above challenges and address the continuing Giga-scale system integration trend. This paper then describes the details behind the design methodology that was used to successfully implement a first-generation CELL processor - a multi-core SoC. Key features of this methodology are broad optimization with fast rule-based analysis engines using macro-level abstraction for constraints propagation up/down the design hierarchy, coupled with accurate transistor level simulation for detailed analysis. The methodology fostered the modular design concept that is inherent to the CELL architecture, enabling a high frequency design by maximizing custom circuit content through re-use, and balanced power, frequency, and die size targets through global convergence capabilities. The design has roughly 241 million transistors implemented in 90 nm SOI technology with 8 levels of copper interconnects and one local interconnect layer. The chip has been tested at various temperatures, voltages, and frequencies. Correct operation has been observed in the lab on first pass silicon at frequencies well over 4GHz.

The design methodology and implementation of a first-generation CELL processor: a multi-core SoC

This paper reviews the design challenges that current and future processors must face with stringent power limits and high frequency targets, and the design methods required to address the continuing system integration trends. This paper then describes the implementation of a first-generation CELL processor and the design methods used to overcome the above challenges. A CELL processor consists of a 64 bit power architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multicore SoC, implemented in 90nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.

A 32b 66 MHz 1.8 W microprocessor

A high-performance 32b CMOS microprocessor with an on-chip cache and low power for functional and standby modes has performance of 26MIPS and dissipates only 1.77 W in functional mode. The features include a 16 b data interface and 24 b address bus, a 16 kB four-way set associative cache, and a clock doubler for operation at 33/66 MHz. The chip is 9/spl times/7.7 mm/sup 2/. It uses single-latch LSSD design and has 99.5% stuck-at fault test coverage.<<ETX>>

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor

The Cell Broadband Engine (Cell BE) is a multicore system-on-chip (SoC), implemented in a 90-nm high-performance silicon-on-insulator (SOI) technology, and optimized, within the triple constraints of area, power, and performance, to run at frequencies in excess of 3 GHz. The large scale of the design (~75 million logic transistors, and about 750 000 latches and flip-flops), high-volume requirements, and the desire to support multiple manufacturing facilities dictated a need for very robust circuit practices, but at the same time, the high-frequency goal drove the use of more aggressive styles in certain critical regions of the design. This paper describes the local clock design, along with the various latches and flip-flops deployed, followed by a discussion of the circuit techniques used for the digital logic implementation, including special considerations for high-speed synthesized control logic, semi-custom and full-custom static circuit design and full-custom dynamic logic circuits. In addition, the synergistic processor element (SPE) circuit design is described, followed by the techniques and issues associated with the SRAM design. Finally, the methods used for electrical verification are described, these being an important part of the strategy for ensuring overall design robustness and first-silicon success

A 3.0 W 75SPECint92 85SPECfp92 superscalar RISC microprocessor

This superscalar microprocessor is a 32b implementation of the PowerPC Architecture. With an estimated performance/power ratio of 25SPECint92/W at 80 MHz, this RISC style chip offers workstation-level performance packed into a low-power consumption, low-cost design ideal for notebooks and desktop computers.<<ETX>>

The design and implementation of a first-generation CELL processor - a multi-core SoC

The implementation of a first-generation CELL processor that supports multiple operating systems including Linux consists of a 64 bit power processor element (PPE) and its L2 cache, multiple synergistic processor elements (SPE) (B. Flachs et al.) each with its own local memory (LS) (T. Asano et al.), a high bandwidth internal element interconnect bus (EIB), two configurable non-coherent I/O interfaces, a memory interface controller (MIC), and a pervasive unit that supports extensive test, monitoring, and debug functions. In conclusion, special circuit techniques, rules for modularity and reuse, customized clocking structures, and unique power and thermal management concepts were applied to optimize the design.

A 1.2 W 66 MHz superscalar RISC microprocessor for set-tops, video games, and PDAs

This 32 b superscalar processor, having 18 mW/MHz projected power consumption at 66 MHz, is designed for desktop companions and high-end embedded multimedia applications with graphics-intensive requirements such as high-performance video games. This processor, the latest member of the PowerPC microprocessor family, can also be used in other low-power computing applications. The processor is fabricated in a 3.3 V, 0.5 m, 4-level metal CMOS resulting in 1 M transistors in a 7.07/spl times/7.07 mm/sup 2/ chip. Dual 4 kB instruction and data caches coupled to a high-performance 64 b multiplexed bus and separate execution units (float, integer, branch, and load-store) result in 2 instructions per clock cycle peak rate. Low-power design includes dynamically-powered-down execution units. Standby power is <2 mW. CPU to bus clock ratios of 2/spl times/ and 3/spl times/ allow control of system power while maintaining processor performance.