Atsuya Okazaki

Optical Interconnect Opportunities for Future Server Memory Systems

This paper deals with alternative server memory architecture options in multicore CPU generations using optically-attached memory systems. Thanks to its large bandwidth-distance product, optical interconnect technology enables CPUs and local memory to be placed meters away from each other without sacrificing bandwidth. This topologically-local but physically-remote main memory attached via an ultra-high-bandwidth parallel optical interconnect can lead to flexible memory architecture options using low-cost commodity memory technologies

Software-defined massive multicore networking via freespace optical interconnect

This paper presents a new frontier where future computer systems can continue to evolve as CMOS technology reaches its fundamental performance and density scaling limits. Our idea adopts freespace circuit-switched optical interconnect in massive multicore networking on chips and modules to flexibly configure private cache-coherent networks for allocated groups of cores in a software-defined manner. The proposed scheme can avoid networking inefficiencies due to the core resource fragmentation by providing deterministically lower latencies and higher bandwidth while advancing the technology roadmap with lower power consumption and improved cooling. We also discuss implementation plan and challenges for our proposal.

Non-intrusive Scalable Memory Access Tracer

Memory access tracing is one of the widely used methods to evaluate, analyze, and optimize hardware and software designs. We are developing a non-intrusive, scalable, full-address-range memory tracer. The tracer hardware board is compliant with the JEDEC DDR3 DIMM form factor, and fits in a DIMM slot. It is so compact that we can populate up to 16 tracer boards in a 4-CPU server chassis, and record the commands and addresses of all the memory accesses. Each board drives four SSDs to record the memory access addresses without a break until the SSDs are full. For example, we can make a trace of a full SPECjbb 2005 run, which lasts 26 minutes and generates over 11TB trace data. In addition to recording memory accesses, it collects various types of statistical data, such as a large number of segmented read/write statistics and DRAM bank utilization rates, and displays them on the control dashboard in real time.

Universal optical multi-drop bus for heterogeneous memory architecture

Emerging non-volatile memory device technologies such as flash, FRAM, and PCM are changing the traditional main memory architecture consisting of DRAM. New architecture-level and OS-level refinements with these memory devices have been proposed. However, in practice, modern high performance processors have difficulties in adding attachment points for new memory interfaces, since the number of off-chip pins are limited due to packaging constraints, and many pins are already in use for existing functions such as SMP links, IO links, and power supplies. In this paper, by taking advantage of optics with multi-drop topology, we propose a novel high-bandwidth low-power memory bus architecture that can connect different memory devices at the same time with a single attachment point on the processor chip. The prototyped 75-Gbps optical multi-drop bus platform can organize DDR2 and DDR3 SDRAM DIMMs on the single bus, and can be attached to a processor with industry-standard 12-ch 250-μm-pitch parallel optical fibers.