Yasunao Katayama

Wireless data center networking with steered-beam mmWave links

This paper presents a new type of wireless networking applications in data centers using steered-beam mmWave links. By taking advantage of clean LOS channels on top of server racks, robust wireless packet-switching network can be built. The transmission latency can be reduced by flexibly bridging adjacent rows of racks wirelessly without using long cables and multiple switches. Eliminating cables and switches also reduces equipment costs as well as server installation and reconfiguration costs. Security can be physically enhanced with controlled directivity and negligible wall penetration. The aggregate data transmission BW per given volume is expected to scale as the fourth power of carrier frequency. The paper also deals with the architecture of such network configurations and a preliminary demonstration system.

Fault-tolerant refresh power reduction of DRAMs for quasi-nonvolatile data retention

A quasi-nonvolatile memory system based on commercially available low-power dynamic random access memory (DRAM) technology is proposed and demonstrated. By applying a powerful one-shot Reed-Solomon error correction code (ECC) to the data stored in the DRAM, the refresh rate and memory system power usage can be greatly reduced while still maintaining data integrity. An adaptive refresh rate controller was developed in order to ensure robustness against the variations in data retention time due to perturbation effects such as DRAM part-to-part variations, environmental changes and data pattern sensitivity, while at the same time minimizing power usage. By checking for data failures among a small subset of data bits which are dynamically selected at the beginning of each use of the system, the state of the perturbation effects are predicted and used to adjust the refresh rate. As a result, a system was developed that provides reliability equivalent to standard DRAM systems while greatly (10-100X) reducing the refresh power. Experimental results of a test system are presented.

Silicon Millimeter-Wave Radio Circuits at 60-100 GHz

This paper reviews silicon millimeter-wave radio circuits operating between 60 and 100GHz. Transmitter and receiver chips operating in the 60-GHz ISM band are highlighted, where the packaged chipset has shown data rates as high as 2 Gb/s over 5m for a wireless high-definition video link. In addition, a 60GHz PA with 23dBm output power and a class-E 60GHz PA with >20% peak PAE are reviewed. Finally, 77 and 94GHz downconverters are presented as a basis for an outlook to the performance achievable at these higher frequency bands

2-Gbps Uncompressed HDTV Transmission over 60-GHz SiGe Radio Link

We report a proof-of-concept demonstration of 2- Gbps uncompressed HDTV transmission using a 60-GHz SiGe radio chipset. We took a single-carrier approach with a usual DQPSK modulation scheme, assuming an LOS environment, and implemented the system with FPGAs. At the same time, in order to take care of more frequent sync/burst errors in high-data-rate single-carrier approaches, we equipped the baseband with effi- cient random/packet error recovery and symbol-timing recovery with an effective interpolation method. As a result, a clear and crisp image was obtained in the end-to-end transmission. I. INTRODUCTION

Optical Interconnect Opportunities for Future Server Memory Systems

This paper deals with alternative server memory architecture options in multicore CPU generations using optically-attached memory systems. Thanks to its large bandwidth-distance product, optical interconnect technology enables CPUs and local memory to be placed meters away from each other without sacrificing bandwidth. This topologically-local but physically-remote main memory attached via an ultra-high-bandwidth parallel optical interconnect can lead to flexible memory architecture options using low-cost commodity memory technologies

Trends in semiconductor memories

Despite their great market success, DRAMs have not kept pace with microprocessor improvements, so researchers are looking to advanced high-speed DRAM and merged DRAM/logic technologies to increase memory system performance.

Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m)

The Galois field GF(2m) is an important number system that is widely used in applications such as error correction codes (ECC), and complicated combinations of arithmetic operations are performed in those applications. However, few practical formal methods for algorithm verification at the word-level have ever been developed. We have defined a logic system, GF2m -arithmetic, that can treat non-linear and nonconvex constraints, for describing specifications and implementations of arithmetic algorithms over GF(2m). We have investigated various decision techniques for the GF2m -arithmetic and its subclasses, and have performed an automatic correctness proof of a (n, n 4) Reed-Solomon ECC decoding algorithm. Because the correctness criterion is in an efficient subclass of the GF2m -arithmetic (k -field-size independent), the proof is completed in significantly reduced time, less than one second for any m ≥ 3 and n ≥ 5, by using a combination of polynomial division and variable elimination over GF(2m), without using any costly techniques such as factoring or a decision over GF(2) that can easily increase the verification time to more than a day.

MIMO link design strategy for wireless data center applications

This paper deals with mm Wave MIMO link design strategy for wireless data center applications where the MIMO degrees of freedom is taken into account in multi-node packet networking environments. The problem is treated differently from the coordinated multiuser MIMO situation and the link design is optimized independently in each node with meeting control and data plane requirements for contention-based packet switching. In particular, we propose using an interference-aligned out-of-band control plane to improve the unidirectional bonded in-band data plane collision-related performance degradation with a limited number of antenna elements per node. We also present a high-level implementation plan.

OE Device Integration for Optically Enabled MCM

We propose a new architecture of optical device integration on SLC carrier with capability of handling of the optical signals directly on MCM, or an optically enabled MCM, where VCSELs/PDs and the interface chips are placed closer to the main VLSI on a waveguide integrated SLC, while the optical connectors are at the periphery of the SLC carrier. This separated structure allows the highest number of optical channels per periphery length defined by the connector size, as well as the higher optical speed.

Design methodology for a one-shot Reed-Solomon encoder and decoder

The design methodology for a high-performance and compact one-shot Reed-Solomon encoder/decoder realized as a combinational circuit is presented. Under a two-level optimization approach, a combination of new encoding/decoding algorithms enabling highly parallel, yet shared architecture, and logic optimization methods tuned for huge-scale Galois field arithmetic operations, improves the circuit size and speed significantly. The higher level optimization not only can be entirely independent of the gate level optimization, but also further augments the advantages in the gate level optimization. As a result a (40-34,32)RS encoders/decoder soft IP-core achieving 45 ns latency and >7 Gb/s peak throughput without pipelining is realized using <90 K cells under 0.35 um CMOS gate-array technology.