Atul Garg

A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's

A digital voltage-controlled oscillator (VCO) is described which uses frequency multiplication and division to achieve very wide bandwidth. The VCO uses current-mode logic and does not require reactive elements such as inductors, capacitors or varactors. A novel, fully symmetric exclusive-OR (XOR) circuit was developed which uses product pairs and emitter-coupled logic. To achieve the highest performance possible, the critical path is symmetric and special physical design techniques were developed to promote matched-capacitance. The maximum measured frequency was 13.66 GHz. The chip occupies 1.9 mm/spl times/1.6 mm and dissipates 2.45 W at a supply voltage of -6.0 V. With a measured frequency range from 1.25 to 13.66 GHz, this circuit has the widest bandwidth reported in the literature for any VCO, digital or analog.

A very-wide bandwidth digital VCO implemented in GaAs HBTs using frequency multiplication and division

A digital high-speed voltage-controlled oscillator (VCO) has been developed which uses frequency-multiplication and division to attain a wide frequency range of 0.5-13.66 GHz. The circuit is implemented in differential current-mode logic using GaAs-AlGaAs heterojunction bipolar transistors (HBTs). This paper discusses top-level system design as well as the design of several key components.

Embedded at-speed testing schemes with low overhead for high speed digital circuits on multi-chip modules

The difficulty of cost-effectively identifying Known Good Die (KGD) is increased in circuits requiring multiple die packaged in Multi-Chip Modules (MCMs). Such circuits typically have high frequency I/O signals which are difficult to measure using inexpensive test equipment. The cost of full Built-In Self-Test (BIST) can be prohibitive, particularly when device integration levels are low. This paper presents a scheme for testing die for functionality and speed at minimal cost. The scheme also allows testing of MCM traces and testing of on-chip circuits both before and after packaging. The scheme was developed for use in Rensselaer Polytechnic Institutes F-RISC/G 1 ns processor project.

Differential routing of MCMs-CIF: the ideal bifurcation medium

Recently published findings indicate that full differential routing of both VLSI chips and MCMs may be necessary to preserve noise margins in high performance systems. The optimal differential routing technique relies on routing signal pairs as logical nets and bifurcating the results to achieve a physical realization. Based on our research, CIF (Caltech. Interchange Format) has emerged as the ideal medium for the bifurcation process associated with differential routing of MCMs. Since MCMs have not as yet fully come of age, many of their design variables are under constrained. One of the greatest strengths of our finding is CIFs ability to handle the design uncertainty associated with current MCM system development, where both package and chip specification are typically in a tremendous state of flux throughout the engineering design cycle.<<ETX>>

Design of a package for a high-speed processor made with yield-limited technology

The design of an advanced high density thin film multichip module (MCM) for a 1-ns cycle time Fast Reduced Instruction Set Computer (F-RISC/G) is described. The processor has been implemented with GaAs/AlGaAs heterojunction bipolar transistor (HBT) technology from Rockwell International. The F-RISC/G package pushes the state of the art to satisfy electrical, thermal and thermomechanical constraints to take advantage of this high speed circuit technology. A unique approach is developed to link the electrical and thermomechanical design environments using a common database.<<ETX>>

Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy

Integrated-circuit interconnect characterization is growing in importance as devices become faster and smaller. Along with this trend, interconnect geometry is becoming more complex, consisting of an increasing number of wiring levels. Accurate numerical extraction of three-dimensional (3-D) interconnect capacitance is essential for achieving design targets in the multigigahertz digital regime. Interconnect-capacitance extraction is complicated by the presence of inhomogeneous layers with differing dielectric constant. Dielectric anisotropy as well is common in many low-/spl kappa/ polymeric dielectrics used in high-performance ICs. A CAD procedure using the novel floating random-walk extractor QuickCAP is presented. Our procedure is efficient enough to extract a substantial amount of a chips 3-D wiring. We include as well dielectric anisotropy and inhomogeneity. The procedure is not based on effective conductor geometry or on a finite-sized conductor library but rather on the entire 3-D layout, accounting for actual local variations in conductor separations and shapes. We then apply our procedure to an experimental circuit vehicle implemented in AlGaAs-GaAs heterojunction bipolar transistor current-mode logic. This vehicle is used to validate the accuracy of our CAD procedure in predicting circuit speed. Measured and predicted test-capacitor values and ring-oscillator propagation times agreed generally to within 2-4%. To verify results on a larger digital circuit, we analyzed all interconnects in an adder carry-chain oscillator using our procedure. Predicted propagation delays were generally within 3% of measurement.

Thermal design of an advanced multichip module for a RISC processor

Multichip module (MCM) technology is attracting attention from designers who need high-speed interchip connections and a reliable package for their circuit applications. This technology is being applied to realize a 1-ns cycle time 32-bit RISC processor, using 50 GHz AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology and triple-level full-differential current mode logic (CML), at Rensselaer. The processor is partitioned into multiple chips due to the high power consumption and low integration level of the technology. There are several key challenges associated with this module. It has to provide high-bandwidth (/spl les/10 GHz) and high-density (/spl les/40 /spl mu/m pitch) interconnect, and dissipate nearly 250 W of power. Maximum heat flux on the MCM surface is 2.0/spl times/10/sup 5/ W/m/sup 2/. Poor heat conduction ability of GaAs chips make it tough to dissipate this hear. A methodology is developed to design a thermally stable module using a multilayer substrate with parylene as a low dielectric constant insulator, and fine pitch copper for high bandwidth lines. The design of the MCM and the thermal simulation results are presented.<<ETX>>

Wiring pitch integrates MCM design domains

MCM designs require independent analysis in loosely coupled but interrelated design regimes. This paper proposes wiring pitch as the unifying thread in a real time iterative design environment that facilitates analysis in all pertinent domains. Actual system results demonstrate the strengths of the technique.<<ETX>>

Programmable Logic Devices

The sections in this article are 1 Programmable-Logic Device Architectures 2 Applications 3 Conclusion

Measurement and modeling of high-speed interconnect-limited digital ring oscillators: The effect of dielectric anisotropy

IC interconnect characterization is growing in importance as devices become faster and smaller. Accurate numerical extraction of 3D interconnect capacitance is essential for achieving design targets in the multi-GHz digital regime. An AlGaAs-GaAs heterojunction-bipolar-transistor test chip was fabricated. The chip used 3-level metal with anisotropic polyimide interlevel dielectrics. Full differential current-mode logic circuit technology was employed. The chip contained a variety of interconnect capacitor structures (parallel plate, finger, crossover) and interconnect-limited ring-oscillator circuits. Capacitance and oscillator frequency measurements were performed to compare with CAD-tool predictions. Good agreement with measurements was achieved with an independently obtained 25% uniaxial polyimide dielectric anisotropy. Measured and predicted results for the capacitor test structures generally agreed to within 2%. Predicted ring-oscillator periods were within 4% of measurement.