Hans J. Greub

Performance of random-walk capacitance extractors for IC interconnects: A numerical study

Abstract With ever-shrinking feature geometries, multilevel IC interconnects will greatly influence overall circuit behavior. In particular, efficient numerical evaluation of 3D IC-interconnect capacitance is essential to achieving targeted design goals. Previously, we have reported a new random-walk (RW) algorithm for extracting capacitance of complex multilevel IC interconnects [see, Y.L. Le Coz and R.B. Iverson, Solid-St. Electron. 35, 1005 (1991)]. Here, for the first time, we present a numerical study concerning the influence of interconnect complexity on RW-extractor performance. Of primary interest, are the empirical relationships among geometric complexity, run time, and memory usage. We also include, for reference, comparisons with conventional finite-element (FE) and boundary-element (BI) capacitance extractors. Despite the general computational limitations of these conventional extractors, we have attempted to normalize numerical errors to a single common value. The problem geometry selected for our study consists of a long “bus” wire situated beneath a series of shorter cross wires. Problem complexity is controlled by increasing the bus-wire length and adding cross wires. We have found that at 1% normalized error in bus-wire self-capacitance, the RW extractor has the shortest execution time, which is uniquely independent of problem complexity. In addition, because the RW extractor requires no numerical meshing, an RW:BI:FE memory-usage ratio of 1:103:107 was observed. We conclude that the RW method may possibly excel in the high-complexity regime characteristic of multilevel IC interconnects.

High-performance standard cell library and modeling technique for differential advanced bipolar current tree logic

A high-performance standard cell library for the Tektronix advanced bipolar process GST1 has been developed. The library is targeted for the 250-MIPS (million instructions per second) fast reduced instruction set computer (FRISC) project. The GST1 devices have a minimal emitter size of 0.6 mu m*2.4 mu m and a maximum f/sub t/ of 15.5 GHz. By combining advanced bipolar technology and high-speed differential logic, gate propagation delays of 90 ps can be achieved at a power dissipation of 70 mW. The fastest buffers/inverters have a propagation delay of only 68 ps. A 32-b ALU (arithmetic and logic unit) partitioned into four slices can perform an addition in 3 ns using differential standard cells with improved emitter-follower outputs and fast differential I/O drivers. A modeling technique for high-speed differential current tree logic is introduced. The technique gives accurate timing information and models the transient behavior of current trees. >

A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's

A digital voltage-controlled oscillator (VCO) is described which uses frequency multiplication and division to achieve very wide bandwidth. The VCO uses current-mode logic and does not require reactive elements such as inductors, capacitors or varactors. A novel, fully symmetric exclusive-OR (XOR) circuit was developed which uses product pairs and emitter-coupled logic. To achieve the highest performance possible, the critical path is symmetric and special physical design techniques were developed to promote matched-capacitance. The maximum measured frequency was 13.66 GHz. The chip occupies 1.9 mm/spl times/1.6 mm and dissipates 2.45 W at a supply voltage of -6.0 V. With a measured frequency range from 1.25 to 13.66 GHz, this circuit has the widest bandwidth reported in the literature for any VCO, digital or analog.

A very-wide bandwidth digital VCO implemented in GaAs HBTs using frequency multiplication and division

A digital high-speed voltage-controlled oscillator (VCO) has been developed which uses frequency-multiplication and division to attain a wide frequency range of 0.5-13.66 GHz. The circuit is implemented in differential current-mode logic using GaAs-AlGaAs heterojunction bipolar transistors (HBTs). This paper discusses top-level system design as well as the design of several key components.

F-RISC/G: AlGaAs/GaAs HBT standard cell library

A standard cell library for implementing Rensselaers fast reduced instruction set computer (F-RISC/G) project with Rockwells AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology is presented. The processor is targeted at an instruction cycle time of 1.0 ns. Differential current mode logic (CML) is used, and unloaded gate delays are 15-20 ps.<<ETX>>

Key components of the fast reduced instruction set computer (FRISC) employing advanced bipolar differential logic and wafer scale multichip packaging

Advanced bipolar circuits for a RISC operating at a 250 MHz instruction rate are presented. Specifically a 30*8 bit register file macro with 500-ps access time is presented and a clock skew compensation scheme based on digital delay lines is introduced that can significantly reduce clock skew in a wafer scale multichip package. The predicted performance of advanced bipolar memory macros, I/O circuitry, and differential logic circuit are very encouraging. Measurement on a fabricated divide by two circuits shows good agreement with SPICE simulations.<<ETX>>

Embedded at-speed testing schemes with low overhead for high speed digital circuits on multi-chip modules

The difficulty of cost-effectively identifying Known Good Die (KGD) is increased in circuits requiring multiple die packaged in Multi-Chip Modules (MCMs). Such circuits typically have high frequency I/O signals which are difficult to measure using inexpensive test equipment. The cost of full Built-In Self-Test (BIST) can be prohibitive, particularly when device integration levels are low. This paper presents a scheme for testing die for functionality and speed at minimal cost. The scheme also allows testing of MCM traces and testing of on-chip circuits both before and after packaging. The scheme was developed for use in Rensselaer Polytechnic Institutes F-RISC/G 1 ns processor project.

Design of a package for a high-speed processor made with yield-limited technology

The design of an advanced high density thin film multichip module (MCM) for a 1-ns cycle time Fast Reduced Instruction Set Computer (F-RISC/G) is described. The processor has been implemented with GaAs/AlGaAs heterojunction bipolar transistor (HBT) technology from Rockwell International. The F-RISC/G package pushes the state of the art to satisfy electrical, thermal and thermomechanical constraints to take advantage of this high speed circuit technology. A unique approach is developed to link the electrical and thermomechanical design environments using a common database.<<ETX>>

Wideband wafer-scale interconnections in a wafer scale hybrid package for a 1000 MIPS highly pipelined GaAs/AlGaAs HBT RISC

A wideband thin-film wafer scale hybrid package (WSHP) or multi-chip module (MCM) will be used to interconnect the chips of a high-performance RISC (reduced instruction set computer) architecture developed at Rensselaer. This architecture is being implemented using GaAs/AlGaAs heterojunction bipolar transistors (HBTs) and triple-level differential current-mode logic. Because of high power consumption yield limitations of the HBT technology, the processor is partitioned into multiple chips. These chips must be connected using lines capable of handling the fast rise-time signals. Also, the MCM must contain integrated bypass capacitors and termination resistors.<<ETX>>

F-RISC/I: fast reduced instruction set computer with GaAs (H) MESFET implementation

F-RISC/I is a monolithic GaAs microprocessor with a seven stage pipeline implemented with SBFL standard cells. It is targeted at a clock rate of 400 MHz with a CPI of 1.45. The impacts of GaAs technology on system architecture, CPU architecture, circuit level optimization, implementation, performance, and testing of F-RISC/I are discussed. The GaAs technology environment is investigated and compared to that of Si.<<ETX>>