Avijit Saha

Approximation, dimension reduction, and nonconvex optimization using linear superpositions of Gaussians

This paper concerns neural network approaches to function approximation and optimization using linear superposition of Gaussians (or what are popularly known as radial basis function (RBF) networks). The problem of function approximation is one of estimating an underlying function f, given samples of the form ((y/sub i/, x/sub i/); i=1,2,...,n; with y/sub i/=f(x/sub i/)). When the dimension of the input is high and the number of samples small, estimation of the function becomes difficult due to the sparsity of samples in local regions. The authors find that this problem of high dimensionality can be overcome to some extent by using linear transformations of the input in the Gaussian kernels. Such transformations induce intrinsic dimension reduction, and can be exploited for identifying key factors of the input and for the phase space reconstruction of dynamical systems, without explicitly computing the dimension and delay. They present a generalization that uses multiple linear projections onto scalars and successive RBF networks (MLPRBF) that estimate the function based on these scaler values. They derive some key properties of RBF networks that provide suitable grounds for implementing efficient search strategies for nonconvex optimization within the same framework. >

Multiprocessor system verification through behavioral modeling and simulation

The long development times and high costs of multiprocessor (MP) designs arise from their design complexity. To reduce the time and costs, it is critical that design bugs are detected early in the development cycle using design verification tools. The traditional method of hardware design verification is to simulate the actual hardware designs, usually specified in a hardware description language such as VHDL. Two major drawbacks of this methodology when applied to MP systems are the huge size of MP models and the long simulation times. In addition to the difficulty of detecting incorrect behavior in hardware cache coherent systems, MP system verification presents many other challenges as well. In this paper we present a MP verification methodology that lets the actual hardware designs coexist with behavioral models that approximate the functional behavior of the designs they represent. We describe an event-driven behavioral simulation engine that drives the entire simulation, an MP test language, a test executive that injects new transactions into the system, and a coherence monitor that helps detect quickly and efficiently coherency-related bugs in hardware designs.<<ETX>>

Causality based generation of directed test cases

Simulation is considered to be the irreplaceable part of design verification. However, the efficiency of this method depends greatly on the test cases used. Random test cases can be generated quickly but have poor coverage. Directed test cases on the other hand require time and manual effort. This paper presents a method for generating directed test cases automatically by making use of signal relationships in the specification. An algorithm is presented that was applied to the GL85 microprocessor, a clone of Intels 8085. The results are compared with other methods to see the gain with the proposed method.

Distributed directory tags

This paper concerns a new directory scheme that can be used as an alternative to the current three types of directory schemes; direct mapped, set associative and fully associative. Both direct mapped and fully associative cache directories can be considered as a special case of the set associative directory since in the direct mapped case there are N congruent classes with a set size of 1 while in the fully associative case there are N sets and only 1 congruent class. However, irrespective of which class of directory scheme is used, since memory or cache directories generally provide a many-to-one mapping of a large address space to a small fast storage, a tag field must be associated with each element to identify one of the many addresses which actually map to the current value in the cache element. Thus, there are as many tags as there are total elements in the directory. The Distributed Directory Tag scheme described here uses the direct mapping of the addresses and distribution of the tags over the directory elements and thereby reduces the storage requirement for the directory tags by a significant factor. Our early findings indicate that addresses from application programs follow a particular distribution, with a strong bias towards less frequent change in the higher order bits. It is this observation that is exploited in the scheme described in this paper. The actual savings depend on the particular distribution chosen for an implementation, but in general, a factor of three reduction can be obtained while providing a hit ratio comparable to the other directory schemes. This savings in the tag bits is achieved while still providing set associativity within each congruent class. This scheme is particularly useful when cost/performance tradeoffs are a consideration. Thus, this novel directory design adds another type to the three existing cache directory schemes.