Brian O'krafka

A simulation-based approach to architectural verification of multiprocessor systems

This paper presents a simulation-based method for verifying coherency in weakly ordered shared memory multiprocessor systems. This methodology requires minimal assumptions regarding the implementation details, such as the coherence protocol and cache line replacement rules. Independence from implementation details for architectural verification is achieved via a technique called data-coloring. The non-determinism arising from weak ordering is resolved by introducing the notion of valid sets for checking the correctness of memory operations. We contrast our approach with other methods that have been prevalent in the industry and provide implementation details and an example implementation of our methodology.<<ETX>>

MPTG: a portable test generator for cache-coherent multiprocessors

Cache-coherent multiprocessors are typically verified by extensive simulation with randomly generated testcases. With this methodology, certain aspects of test coverage can be measured using monitors that record the occurrence of specific events during simulation. If certain events do not occur sufficiently often, the designer must somehow bias the random test generator or write hand-written testcases to improve coverage of the desired event. This is usually a labor-intensive process that is made worse by frequent changes in design specifications and the high cost of simulating large multiprocessor models. This paper describes MPTG (MultiProcessor Test Generator): a portable test generator that automates much of this labor-intensive component of the simulation process. MPTG does this by deterministically generating sets of testcases that are guaranteed to cause specific events to happen. For example, with a single, compact test specification it is possible to generate a set of tests that exercise all transaction types and current cache state combinations at a particular cache in the system. Alternatively, it is easy to generate a set of tests that exercise all two-way races that can occur at a particular cache. Test generation at this level of detail requires the incorporation of a system-wide coherence protocol within the test generator, which can make it difficult to port the test generator to different systems. Portability is achieved in MPTG by breaking the test generator into two parts: a generic test generation engine and a system-specific set of protocol tables.<<ETX>>

Multiprocessor system verification through behavioral modeling and simulation

The long development times and high costs of multiprocessor (MP) designs arise from their design complexity. To reduce the time and costs, it is critical that design bugs are detected early in the development cycle using design verification tools. The traditional method of hardware design verification is to simulate the actual hardware designs, usually specified in a hardware description language such as VHDL. Two major drawbacks of this methodology when applied to MP systems are the huge size of MP models and the long simulation times. In addition to the difficulty of detecting incorrect behavior in hardware cache coherent systems, MP system verification presents many other challenges as well. In this paper we present a MP verification methodology that lets the actual hardware designs coexist with behavioral models that approximate the functional behavior of the designs they represent. We describe an event-driven behavioral simulation engine that drives the entire simulation, an MP test language, a test executive that injects new transactions into the system, and a coherence monitor that helps detect quickly and efficiently coherency-related bugs in hardware designs.<<ETX>>