Avirup Dasgupta

Surface-Potential-Based Compact Modeling of Gate Current in AlGaN/GaN HEMTs

In this paper, the gate current in AlGaN/GaN high-electron mobility transistors is modeled analytically in a surface potential-based compact model. Thermionic emission and Poole-Frenkel emission are two dominant mechanisms for the gate current in the forward and reverse-bias regions, respectively. In addition, a trap-assisted tunneling component, which is important at low reverse bias, is also added. The developed gate current model, implemented in Verilog-A is in excellent agreement with experimental data and passes the important Gummel symmetry test.

Capacitance Modeling in Dual Field-Plate Power GaN HEMT for Accurate Switching Behavior

In this paper, a surface-potential-based compact model is proposed for the capacitance of an AlGaN/GaN high-electron mobility transistor (HEMT) dual field-plate (FP) structure, i.e., with gate and source FPs. FP incorporation in a HEMT gives an improvement in terms of enhanced breakdown voltage, reduced gate leakage, and so on, but it affects the capacitive nature of the device, particularly by bringing into existence in a subthreshold region of operation, a feedback miller capacitance between the gate and the drain, and also a capacitance between the drain and the source, therefore, affecting switching characteristics. Here, we model the bias dependence of the terminal capacitances, wherein the expressions developed for intrinsic charges required for capacitance derivation are analytical and physics-based in nature and valid for all regions of device operation. The proposed model, implemented in Verilog-A, is in excellent agreement with the measured data for different temperatures.

Surface Potential Based Modeling of Thermal Noise for HEMT Circuit Simulation

In this letter, an analytical surface potential based compact model for thermal noise in high electron mobility transistors (HEMTs) is presented. The model is based on the recently proposed surface potential formulation for charges and current. The model is tunable and applicable to any HEMT device.

Compact Modeling of Flicker Noise in HEMTs

In this paper, we present a physics-based compact model for low frequency noise in high electron mobility transistors (HEMTs). The model is derived considering the physical mechanisms of carrier number fluctuation and mobility fluctuation in the channel. The model is tunable and hence applicable to a wide range of HEMT devices of different geometries and construction. The model is in excellent agreement with experimental data and TCAD simulations.

Compact Modeling of Surface Potential, Charge, and Current in Nanoscale Transistors Under Quasi-Ballistic Regime

In this paper, we have proposed a new analytical model for FETs working in the quasi-ballistic regime. The model is based on a calculation of the charge density along the channel which is then used to solve Poissons equation to get the variation of the channel potential. This is then used to calculate the ballistic and drift-diffusive components of the current. The model is capable of accurately predicting the terminal I-V characteristics for all drain and gate biases and includes short-channel effects. It takes length scaling into account and can be used for the full range of devices starting from complete drift diffusive to completely ballistic. The model has been verified with data for high electron mobility transistors (degenerate) and common multigate and nanowire FETs (nondegenerate) proving its ability to take different geometries into consideration. It can be easily implemented as a compact model and used for SPICE circuit simulations.

BSIM-CMG: Standard FinFET compact model for advanced circuit design

This work presents new compact models that capture advanced physical effects presented in industry FinFETs. The presented models are introduced into the industry standard compact model BSIM-CMG. The core model is updated with a new unified FinFET model, which calculates charges and currents of transistors with complex fin cross-sections. In addition, threshold voltage modulation from bulk-bias effects and bias dependent quantum mechanical confinement effects are incorporated into the new core model. Short channel effects, affecting threshold voltage and subhtreshold swing, are modeled with a new unified field penetration length, enabling accurate 14nm node FinFET modeling. The new proposed models further assure the BSIM-CMG models capabilities for circuit design using FinFET transistors for advanced technology nodes.

Characterization of RF Noise in UTBB FD-SOI MOSFET

In this paper, we report the noise measurements in the RF frequency range for ultrathin body and thin buried oxide fully depleted silicon on insulator (FD-SOI) transistors. We analyze the impact of back and front gate biases on the various noise parameters; along with discussions on the secondary effects in FD-SOI transistors which contribute to the thermal noise. Using calibrated TCAD simulations, we show that the noise figure changes with the substrate doping and buried oxide thickness.

Unified Compact Model for Nanowire Transistors Including Quantum Effects and Quasi-Ballistic Transport

We present a surface potential-based compact model for nanowire FETs, which considers 1-D electrostatics along with the effect of multiple energy subbands. The model is valid for any semiconductor material, cross-sectional geometry, and any channel length with transport regimes varying from drift-diffusive to quasi-ballistic. The model captures the phenomenon of quantum capacitance and the effect of temperature. We have validated it with numerical simulations and experimental data for Si, Ge, and InAs nanowires of different geometries. Circuit simulation has also been performed with the model. The physics-based model is accurate and can be used as a tool for analysis and prediction of the effects of geometry scaling, material dependence, and temperature variation on device and circuit characteristics. To the best of our knowledge, this is the first time a compact model for nanowire FETs is being presented, which includes multiple subbands along with geometry scaling while being valid for different degenerate and nondegenerate semiconductor materials.

Effect of access region and field plate on capacitance behavior of GaN HEMT

Incorporation of Field Plate in High Electron Mobility Transistors (HEMTs) improves the device breakdown voltage but on the other hand, increases the device Capacitance. It has a direct impact on the device switching characteristics and hence the study of the capacitive behavior holds supreme importance for GaN HEMTs power switching application. Also, in GaN HEMTs, lower values of access region resistance improves the device output current but at the cost of increase in its capacitance, CGD. In this paper, using TCAD simulations on a field plated GaN HEMT, we present the physical explanation for the variation in C-V characteristics for different access region and field plate lengths.

ASM-HEMT: Compact model for GaN HEMTs

In this paper, we aim to present the Advances Spice Model for High Electron Mobility Transistors (ASM-HEMT). The model is currently being considered in the second phase of industry standardization by the Compact Model Coalition (CMC). The presented physical model is surface potential based and is computationally efficient by virtue of being completely analytical. It includes velocity saturation effects, access region resistance effects, DIBL, temperature dependance and models for gate current and noise. The model has been rigorously tested on measured data, and shows good match.