Yogesh Singh Chauhan

BSIM—SPICE Models Enable FinFET and UTB IC Designs

Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is developed to simulate double-, triple-, and all-around-gate FinFETs and it is selected as the worlds first industry-standard compact model for the FinFET. The BSIM-IMG (independent-multigate) model is developed for independent double-gate, ultrathin body (UTB) transistors, capturing the dynamic threshold voltage adjustment with back gate bias. Starting from long-channel devices, the basic models are first obtained using a Poisson-carrier transport approach. The basic models agree with the results of numerical two-dimensional device simulators. The real-device effects then augment the basic models. All the important real-device effects, such as short-channel effects (SCEs), quantum mechanical confinement effects, mobility degradation, and parasitics are included in the models. BSIM-CMG and BSIM-IMG have been validated with hardware silicon-based data from multiple technologies. The developed models also meet the stringent quality assurance tests expected of production level models.

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.

Analytical Modeling of Surface-Potential and Intrinsic Charges in AlGaN/GaN HEMT Devices

A surface potential (SP)-based analytical model for intrinsic charges in AlGaN/GaN high electron mobility transistor devices is presented. We have developed a precise analytical method to calculate the Fermi-level position Ef from a consistent solution of Schrodingers and Poissons equations in the quantum well, considering the two important energy levels. The accuracy of our Ef calculation is on the order of femto-volts for the full range of bias voltage. The SP calculated from Ef is used to derive an analytical model for intrinsic charges in these devices. The model is in excellent agreement with experimental data.

BSIM6: Analog and RF Compact Model for Bulk MOSFET

BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node.

Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design

We present an accurate and robust surface-potential-based compact model for simulation of circuits designed with GaN-based high-electron mobility transistors (GaN HEMTs). An accurate analytical surface-potential calculation, which we developed, is used to develop the drain and gate current model. The model is in excellent agreement with experimental data for both drain and gate current in all regions of device operation. We show the correct physical behavior and mathematical robustness of the model by performing various benchmark tests, such as DC and AC symmetry tests, reciprocity test, and harmonic balance simulations test. To the best of our knowledge, this is the first time a GaN HEMT compact model passing a range of benchmark tests has been presented.

Compact Modeling of Lateral Nonuniform Doping in High-Voltage MOSFETs

This paper reports on the detailed analysis and modeling of lateral nonuniform doping present in intrinsic MOS channel of high-voltage (HV) MOSFETs, e.g., vertical (VDMOS) and lateral diffused MOS (LDMOS). It is shown that conventional long-channel MOSFET models using uniform lateral doping can never correctly model the capacitance behavior of these devices. A new analytical compact model for lateral nonuniformly doped MOSFET is reported. The intrinsic nonuniformly doped MOS model is first validated on numerical simulation and then on measured characteristics of VDMOS and LDMOS transistors including the drift region. The model shows good results in the dc and, most importantly, in the ac regime, especially in simulating the peaks on CGD, CGS, and CGG capacitances. This new model improves the accuracy of HV MOS models, especially output characteristics and during transient response (i.e., amplitude and position of peaks, as well as slope of capacitances).

Analysis and Modeling of Lateral Non-Uniform Doping in High-Voltage MOSFETs

This paper reports on the impact and modeling of lateral doping gradient present in the intrinsic MOS channel of high voltage MOSFETs e.g. VDMOS and LDMOS. It is shown that the conventional MOSFET models using uniform lateral doping can never correctly model the capacitance behavior of these devices. A new charge-based analytical compact model for lateral non-uniformly doped MOSFET is reported. The model is validated on the measured characteristics of VDMOS and LDMOS transistors. The model shows good results in DC and, most importantly in AC regime, especially in simulating the peaks in CGD, CGS and CGG capacitances. This new model improves the accuracy of high voltage MOS models, especially output characteristics and during transient response (i.e. amplitude and position of peaks as well as slope of capacitances)

Thickness and electric-field-dependent polarizability and dielectric constant in phosphorene

Based on extensive first-principles calculations, we explore the thickness-dependent effective dielectric constant and slab polarizability of few-layer black phosphorene. We find that the dielectric constant in ultrathin phosphorene is thickness-dependent and it can be further tuned by applying an out-of-plane electric field. The decreasing dielectric constant with reducing number of layers of phosphorene is a direct consequence of the lower permittivity of the outer layers and the increasing surface-to-volume ratio. We also show that the slab polarizability depends linearly on the number of layers, implying a nearly constant polarizability per phosphorus atom. Our calculation of the thickness- and electric-field-dependent dielectric properties will be useful for designing and interpreting transport experiments in gated phosphorene devices, wherever electrostatic effects such as capacitance and charge screening are important.

Surface-Potential-Based Compact Modeling of Gate Current in AlGaN/GaN HEMTs

In this paper, the gate current in AlGaN/GaN high-electron mobility transistors is modeled analytically in a surface potential-based compact model. Thermionic emission and Poole-Frenkel emission are two dominant mechanisms for the gate current in the forward and reverse-bias regions, respectively. In addition, a trap-assisted tunneling component, which is important at low reverse bias, is also added. The developed gate current model, implemented in Verilog-A is in excellent agreement with experimental data and passes the important Gummel symmetry test.

Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs

In this letter, we present a thermal network extraction methodology to characterize self-heating effect using two-port RF measurements. We show the technique of determining isothermal condition using only the self-heating (thermal) dominated range of the spectrum. We use a self-consistent self-heating extraction scheme using both the real and imaginary parts of drain port admittance parameters. Appropriate thermal network is investigated, and a large amount of temperature rise due to self-heating is confirmed for short channel silicon-on-insulator MOSFETs with ultrathin body and buried oxide.