Avni Morgül

Implementation of Multi-Valued Logic Gates Using Full Current-Mode CMOS Circuits

In this paper, a novel multi-valued logic gate set is designed by using only current-mode CMOS circuits. The gate set consists of min, max, inverter, literal, and cyclic operators based on a current-mode, versatile, novel threshold topology. They are shown to exhibit better static and dynamic behavior and consume less area compared to previous MVL design topologies and binary-logic counterparts. The gate circuits are investigated in terms of analog design aspects, such as mismatch and noise. The proposed topology is compared to previous topologies in terms of attainable radix and DC characteristics. A radix-8 multiplex function and a radix-8 full-adder circuit is designed to demonstrate the advantages of new current-mode multi-valued logic circuits.

Multi-valued logic function implementation with novel current-mode logic gates

In this paper, a novel multi-valued logic gate set is implemented using current-mode CMOS circuits. The gate set consists of min, max, inverter, and literal operators. They are shown to exhibit superior static and dynamic behavior and consume less area compared to their binary-logic counterparts. The advantages of current-mode multi-valued logic design are demonstrated with some applications, such as a radix-8 multiplexer and full adder circuits.

Wideband self-biased CMOS CCII

Wideband, self-biased, second generation current conveyor (CCII) is proposed. It is shown that the proposed CCII exhibits superior performance compared to its previous counterparts in terms of bandwidth, parasitic resistance and voltage swing on port X. Also, the proposed CCII uses no additional biasing voltage or current sources other than the two supply rails.

SELF-BIASING CURRENT CONVEYOR FOR HIGH FREQUENCY APPLICATIONS

A new, self-biasing, differential pair-based and high performance CMOS CCII circuit is proposed which uses no additional biasing voltage or current sources other than the two supply rails. The proposed circuit has high voltage swings on ports X and Y, very low equivalent impedance on port X, high equivalent impedances on ports Y and Z and also wideband voltage and current transfer ratios. The noise analysis of the proposed CCII circuit is studied. Input referred noise voltage at high impedance port Y and input referred noise current at low impedance port X are obtained to form the noise model. Some filter circuits are selected from the literature and their noise comparisons are performed. It is shown that the noise values can differ greatly even though the filter circuits or the passive element values are identical.

A novel signed higher-radix full-adder algorithm and implementation with current-mode multi-valued logic circuits

A higher-radix algebra for full-addition of two numbers is described and realised by combining multivalued logic min, max, literal and cyclic operators in terms disjoint terms. The latter operator is designed by using a current-mode threshold circuit while the other operator is realised by only voltage-mode switching circuits. The threshold circuit employed allows for much higher radices compared to architectures employing voltage-mode binary logic switching circuits as well as better mismatch properties compared to previous threshold circuits. Due to disjoint terms involved, multi-valued logic min and max operators can be replaced with ordinary transmission operation and addition, respectively. Resultant a single-digit, radix-8 full-adder and its 3-bit counterpart voltage-mode circuits are realised and compared. The algorithm is also exploited for a multi-digit case and its HSPICE simulation results are presented.

On the realization of high performance current conveyors and their applications

In this work, a wideband and high-performance CMOS implementation of 2nd-generation current conveyor (CCII) is proposed. The proposed circuit is composed of a high performance voltage follower stag...

Wide-band hybrid analog/Digital frequency domain adaptive filter

This paper describes a hybrid adaptive filter which employs a cascade of analog forward and inverse Fourier transform processors interconnected via a digital interface. The interface multiplies the transformed input, sample by sample, by a set of weights stored in RAM and compares the products against a desired complex spectrum. The resulting error is used to update the RAM weights via a feedback loop, which forces the multiplied output to converge towards the desired complex spectrum. The use of frequency domain processing in the adaptive filter offers faster, more controlled convergence than conventional time domain adaptive transversal filters. We present simulations and practical results on a frequency domain adaptive filter based on 100 point surface acoustic wave chirp transform processors which give the adaptive filter a 4 MHz real-time bandwidth capability. Thus, this new processor is likely to find potential application in equalization, echo, and interference suppression in high bandwidth communications and radar systems.

Novel multiple function analog filter structures and a dual-mode multifunction filter

This paper reports three multi-function filters each of which realizes at least three basic functions without any external passive elements. Depending on the circuit, from one to four operational transconductance amplifiers (OTAs), and two operational amplifiers (OPAMPs) are employed. All three circuits are transimpedance-mode circuits; one of them can also operate as a current-mode filter. Therefore this filter represents a dual-mode, multifunction filter. The presented theory is verified with macro models in simulation program with integrated circuit emphasis (SPICE) simulations and post layout simulations, which are carried out with parasitics extracted from the layouts of the filter chips.

A new level restoration circuit for multi-valued logic

Compared to binary logic, the multi-valued logic circuits provide very small chip size, higher speed, and considerably small number of interconnections and simpler realization of logic functions. However, the main drawback of these circuits is the lower noise margin. The noise margin decreases as the radix of multi-valued system increases. Due to the low noise margins, it is necessary to restore or recover the nominal levels of the signal after a certain number of cascaded stages. In this paper a new current mode CMOS restoration circuit is presented and evaluated.

A current-mode multi-valued adder circuit for multi-operand addition

Static CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 µm technology. As an example of application, an 8 × 8 bit multiplier circuit is designed and simulated using HSPICE.