Axel G. Braun

Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation

This paper describes the design of an automotive traffic sign recognition application. All stages of the design process, starting on system-level with an abstract, pure functional model down to final hardware/software implementations on an FPGA, are shown. The proposed design flow tackles existing bottlenecks of todays system-level design processes, following an early model-based performance evaluation and analysis strategy, which takes into account hardware, software and real-time operating system aspects. The experiments with the traffic sign recognition application show, that the developed mechanisms are able to identify appropriate system configurations and to provide a seamless link into the underlying implementation flows.

Synthesis of embedded systemC design: a case study of digital neural networks

This work presents the whole system-on-silicon design flow using systemC system specification language. In this study, systemC is used to design a multilayer perceptron neural network, which is applied to an electrocardiogram pattern recognition system. The objective of this work is to exemplify the synthesis of RTL-and behavioral integrated systems. To achieve this, a preprocessing methodology was used to optimize the three main constraints of hardware neural network (HNN) design: accuracy, space and processing speed. This allows a complex HNN to be implemented on a single field programmable gate array (FPGA). The high level systemC synthesis allows the straightforward translation of system level into hardware level, avoiding the error prone and the time consuming translation into another hardware description language.

Coverage Driven Verification applied to Embedded Software

The verification of complex systems, like embedded real time systems as well as SoCs, can not only be considered on hardware module level anymore. The amount of software has increased over the last years and, therefore, the verification of embedded software has got a fundamental importance. One of the main problems in embedded software verification is to stress and cover variables and functions in the embedded software that is already running on microprocessor models, during the design phase. In this paper we present a novel approach to verify embedded software running on a microprocessor model, based on a coverage driven verification technique. We have combined a new application called generic software adapter with a SystemC PowerPC microprocessor model in order to cover difficult corner case scenarios in embedded software. This approach avoids setting several parameters and registers during the initialization when no microprocessor model is used. The embedded software is a case study from the automotive industry which is responsible for controlling read and write requests to a non-volatile memory

SystemC for the Design and Modeling of Programmable Systems

The Field Programmable Logic (FPL) community is set to assume an important role within the electronic system level (ESL) community. Programmable technologies are proving to be the correct implementation substrate for the growing majority of system architects who can no longer afford the cost or shoulder the risks associated with sub-micron ASIC design. In this tutorial we present an overview of SystemC, the dominant and open environment for ESL design and modeling. We focus on presenting the fundamentals of the language and describing an important extension to the language that enables rapid modeling of systems at the transaction level.

Integration of high-level synthesis in ESL platform modeling by automated generation of protocol adapters

In this paper we present an approach for integrating IP components into a general system-level simulation environment by generating tailor-made interfaces and protocol adaptors. With the same methodology we integrate modules modeled for a certain high-level synthesis tool. For modeling systems-on-chip (SoC) interconnects e.g. buses at transaction level we use a generic communication architecture. An essential benefit of our approach is the capability for automatic adaptor generation by mapping component protocols onto a generic protocol which handles communication data and timing. For an independent system integration flow we use the standardized IP exchange format IP-XACT with protocol specific extensions as input for the generation process. In this context we introduce our generic architecture model for component integration in SystemC TLM 2.0 as well.

Checking temporal properties in SystemC specifications

Todays system designs consist of multiple architectural components, software as well as hardware. The ability to specify and verify these systems at a high level of abstraction is a key competence to cope with the increasing design complexity. C/C++ based approaches on system specification and design are becoming more and more important. They provide a common platform for system designers, hardware and software engineers, and allow a high-performant simulation of systems behavior during the whole design process. The leading approach for C++ based system specification is SystemC which is on the step of becoming a de facto standard in industrial system-level design. Generally, within SystemC the testbench of a design will also be specified in SystemC, which results in a tight coupling of the design and the corresponding test environment. On the other hand, only rudimentary testbench support is given in SystemC and sophisticated features of todays testbench environments are missing. The checking of temporal properties is one of the core requirements in the area of functional verification and is not supported by the standard SystemC language. This paper addresses that important problem. It shows strategies for checking temporal properties in a SystemC design in terms of an easy-to-understand application, a traffic light controller.

A case study: systemC-based design of an industrial exposure control unit

This article describes the modeling and refinement process of an industrial application from the automotive domain starting from a C description down to a cycle accurate SystemC model. The work was done within a co-operation between Robert Bosch GmbH, OFFIS Research Laboratory, and the University of Tubingen. The application was given by an exposure control unit from a video sensor system of a Bosch driver assistance application. The objective was to study the design flow, starting from an algorithmic C description down to synthesizable SystemC, which is the starting point for further design activities, e.g. hardware synthesis. The case study includes a comparison of the C and SystemC implementation, an analysis and a discussion of the refinement and implementation process. The fixed-point to integer data type conversion was found to be a critical task within the design process, and an automated solution is provided.

Automated Conversion of SystemC Fixed-Point Data Types

This article describes a methodology for the automated conversion of SystemC fixed-point data types and arithmetics to an integer-based format for simulation acceleration and hardware synthesis. In most design flows the direct synthesis of fixed-point data types and their related arithmetics is not supported. Thus all fixed-point arithmetics have to be converted manually in a very time-consuming and error-prone procedure. Therefore a conversion methodology has been developed and a tool enabling an automated conversion of SystemC fixed-point data types as well as fixed-point arithmetics has been implemented. The article describes the theory and transformation rules of the conversion methodology, their implementation into a tool solution, and its application in terms of an experimental case study.