Joachim Gerlach

The simulation semantics of systemC

We present a rigorous but transparent semantics definition of SystemC that covers method, thread, and clocked thread behavior as well as their interaction with the simulation kernel process. The semantics includes watching statements, signal assignment, and wait statements as they are introduced in SystemC V1.O. We present our definition in form of distributed Abstract State Machines (ASMs) rules reflecting the view given in the SystemC Users Manual and the reference implementation. We mainly see our formal semantics as a concise, unambiguous, high-level specification for SystemC-based implementations and for standardization. Additionally, it can be used as a sound basis to investigate SystemC interoperability with Verilog and VHDL.

System Level Design Using the SystemC Modeling Platform

This paper gives an overview of the SystemC modeling platform and outlines the features supported by the SystemC class library. The use of the modeling platform is shown in terms of an example.

Design of an automotive traffic sign recognition system targeting a multi-core SoC implementation

This paper describes the design of an automotive traffic sign recognition application. All stages of the design process, starting on system-level with an abstract, pure functional model down to final hardware/software implementations on an FPGA, are shown. The proposed design flow tackles existing bottlenecks of todays system-level design processes, following an early model-based performance evaluation and analysis strategy, which takes into account hardware, software and real-time operating system aspects. The experiments with the traffic sign recognition application show, that the developed mechanisms are able to identify appropriate system configurations and to provide a seamless link into the underlying implementation flows.

A methodology for rapid analysis and optimization of embedded systems

The paper describes an environment for the rapid analysis, synthesis and optimization of embedded systems. Since the implementation of these systems is rather complicated, we propose a methodology which automates the entire design flow. Flexibility is achieved by allowing manual intervention which is realized via a modular implementation of algorithms which are being provided. The applicability of the proposed approach is shown in terms of an example (UNIX command grep).

Semiformal verification of temporal properties in automotive hardware dependent software

The verification of embedded software has become an important subject over the last years. This work presents a new semiformal verification approach called SofTPaDS. It combines assertion-based and symbolic simulation approaches for the verification of embedded software with hardware dependencies. SofTPaDS shows to be more efficient than the software model checkers in order to trace deep state spaces and improves the state coverage relative to a simulation-based verification tool. We have successfully applied our approach to an industrial automotive embedded software.

Synthesis of embedded systemC design: a case study of digital neural networks

This work presents the whole system-on-silicon design flow using systemC system specification language. In this study, systemC is used to design a multilayer perceptron neural network, which is applied to an electrocardiogram pattern recognition system. The objective of this work is to exemplify the synthesis of RTL-and behavioral integrated systems. To achieve this, a preprocessing methodology was used to optimize the three main constraints of hardware neural network (HNN) design: accuracy, space and processing speed. This allows a complex HNN to be implemented on a single field programmable gate array (FPGA). The high level systemC synthesis allows the straightforward translation of system level into hardware level, avoiding the error prone and the time consuming translation into another hardware description language.

Coverage Driven Verification applied to Embedded Software

The verification of complex systems, like embedded real time systems as well as SoCs, can not only be considered on hardware module level anymore. The amount of software has increased over the last years and, therefore, the verification of embedded software has got a fundamental importance. One of the main problems in embedded software verification is to stress and cover variables and functions in the embedded software that is already running on microprocessor models, during the design phase. In this paper we present a novel approach to verify embedded software running on a microprocessor model, based on a coverage driven verification technique. We have combined a new application called generic software adapter with a SystemC PowerPC microprocessor model in order to cover difficult corner case scenarios in embedded software. This approach avoids setting several parameters and registers during the initialization when no microprocessor model is used. The embedded software is a case study from the automotive industry which is responsible for controlling read and write requests to a non-volatile memory

A methodology and tool for automated transformational high-level design space exploration

Objective of the methodology presented in this paper is to perform design space exploration on a high level of abstraction by applying high-level transformations. The paper concentrates on algorithmic approaches on controlling the iterative process of transformation selection. A novel modular algorithm for transformation control is presented and its effectiveness is experimentally validated. In combination with a large set of transformation algorithms and mechanisms for high-level estimation of transformation quality, there results a methodology for automated high-level design space exploration. All the concepts are summarized in a software tool called ExTra (Design Space Exploration Using Transformations). Finally, the results of the application of ExTra to the JPEG encoding algorithm are presented.

A scalable methodology for cost estimation in a transformational high-level design space exploration environment

Objective of the methodology presented in this paper is to perform design space exploration on a high level of abstraction by applying high-level transformations. To realize a design loop which is close and settled on upper design levels, a high-level estimation step is integrated. In this paper, several estimation methodologies fixed on different states of the high-level synthesis process are examined with respect to their aptitude on controlling the transformational design space exploration process. Estimation heuristics for several design characteristics are derived and experimentally validated.

On the verification of high-order constraint compliance in IC design

The increasing quality requirements on safety-critical electronic components and the rapid technological progress necessitate the compliance with all specified functional and non-functional design constraints. This paper introduces a novel verification method based on an unified data representation of constraints to enable multi-tool verification tasks. A constraint engineering system is presented which provides flexible, extensible, and multi-tool definitions of complex constraints and high-order verification tasks. Existing verification and simulation tools are combined so that the achieved complexity level of the high-order verification by far exceeds the level of the single tools. The shown examples target practical applications in analog system design and demonstrate the flexibility and the potential of this new verification approach.