Ayad Ghannam

3-D Multilayer Copper Interconnects for High-Performance Monolithic Devices and Passives

This paper presents a new and efficient low-cost multilayer 3-D copper interconnect process for monolithic devices and passives. It relies on the BPN and SU-8 photoresists, associated with an optimized electroplating process to form multilevel 3-D interconnects in a single metallization step. The SU-8 is used as a permanent thick dielectric layer that is patterned underneath specific locations to create the desired 3-D interconnect shape. A 3-D seed layer is deposited above the SU-8 and the substrate to ensure 3-D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized 3-D copper electroplating process is later used to grow 3-D interconnects, ensuring transition between all metallic layers. Finally, high-Q (55 at 5 GHz) power inductors are designed and integrated above a 50 W RF power laterally diffused metal oxide semiconductor device using this process.

Solenoidal transformers for magnetic materials integration

This paper presents the design, fabrication and characterization of suspended solenoidal transformers fabricated using a low cost single step 3D copper electroplating process. The design and optimization of solenoidal transformers with and without magnetic core are performed using HFSS. After optimization, the suspended structures reveal good electrical performance. The addition of a magnetic core to these structures shows a significant improvement of its electrical properties. Thus, an increase of 10% on Gmax, 20% on coupling coefficient k, 80% on the quality factor Q and 350% on the inductance is observed. Under probe measurements carried on the suspended structures without magnetic core exhibit a Gmax of -1.45 dB and a Q of 28.5 at 2.5 GHz. The enhanced performance coupled with the low cost 3D process makes these transformers excellent candidates for todays RF applications.

On-Wafer Measurement Errors Due to Unwanted Radiations on High-Q Inductors

This paper investigates the disagreements that may occur between on-wafer measurements and electromagnetic (EM) simulations of high-Q inductive devices. Such disagreements are highlighted on a planar spiral inductor and a 3-D solenoid which exhibit measured maximum Q-factors of 27 and 35, respectively, while 42 and 45 were expected from EM simulations. Both devices are fabricated on high-resistivity substrates. A radiative interaction is identified between RF probe and inductive device under test. By using EM simulations, extra-losses associated with this parasitic effect are fully modeled through the calculation of radiation and dissipation related Q-factors. Adjustments of on-wafer probe setup are proposed to reduce this parasitic effect. Finally, the 3-D solenoid inductor is characterized using a new experimental fixture, and the maximum Q of 45 predicted by EM simulation is retrieved.

Efficent low cost process for single step metal forming of 3D interconnected above-IC inductors

This paper presents a novel and efficient low cost process capable of integrating high-Q above-IC inductors and their interconnects using a single electroplating step. It relies on the SU8 and BPN resist as well as an optimized electroplating technique to form the 3D interconnected inductor. The SU8 is used to form a thick layer located underneath the inductor to elevate it from the substrate. Then, the BPN is used as a high resolution mold (16:1) for copper electroplating. Standard or time optimized electroplating is later used to grow copper in a 3D manner, making the transition between all metallic layers straight forward. High-Q (55 @ 5 GHz) power inductors have been designed and integrated above an RF power LDMOS device using this process. Finally, the process capabilities are demonstrated by integrating a solenoid inductor using only two lithography masks and a single electroplating step.