Thierry Parra

Transimpedance amplifier-based full low-frequency noise characterization setup for Si/SiGe HBTs

An experimental setup, based on current/voltage conversion through transimpedance amplifiers (TAs), has been implemented for the direct full low-frequency noise (LFN) characterization of Si/SiGe heterojunction bipolar transistors (HBTs) in terms of base and collector short-circuit current noise sources. This setup performs a full characterization, as it measures simultaneously the two noise current sources and their correlation, thanks to an original technique based on the specific properties of a specially designed buffer amplifier using a low-noise common-base bipolar transistor (CB BJT). By means of translation formulae, the obtained measurements are compared with those carried out with a multi-impedance technique. They show a good agreement both for the noise sources spectral densities and for their correlation. The TA-based setup provides enhanced capabilities in terms of measurement speed and remote control potentialities.

On the effects of hot carriers on the RF characteristics of Si/SiGe heterojunction bipolar transistors

This work for the first time experimentally investigates the hot carrier effects on the RF characteristics (up to 30 GHz) of Si/SiGe heterojunction bipolar transistors (HBTs). Reverse base-emitter voltage stresses were applied at room temperature on BiCMOS compatible, sub-micron transistors. The main observed degradation is a decrease of S/sub 21/. It was found that this degradation is minimized (maximized) when biasing at constant collector (base) current. These results may be valuable indications also for degradations induced by ionizing radiations.

A protection circuit for HBT RF Power Amplifier under load mismatch conditions

This paper investigates the radiofrequency failure mechanisms of power amplifier (PA) integrated in an HBT technology, and proposes a circuit solution for PA protection against impedance mismatches. It exposes the failure mechanisms that occur when a PA under extreme conditions (high battery voltage and high input power) is exposed to impedance mismatches at its output. Protection against high voltage operation is addressed by integrating a parallel base resistor which increases significantly emitter collector breakdown. A current sensor is then associated to a feedback loop on the PA biasing circuit that operates when the PA is in high dissipated power conditions by limiting the collector current. These protections are easily implemented on the PA die without any extra area. Experiments confirm the effectiveness of these principles: the protection is indexed on the collector supply voltage and acts for all output loads leading to VSWR up to 1 0:1, whereas output power and power efficiency on a 50 Omega load are not affected.

Integrated Schottky Diodes for sub-millimeter and THz passive imaging: Influence of detector arrays topology

This work investigates Silicon-based passive detectors in sub-millimeter and terahertz frequency range for imaging applications. Comparison of detection mechanisms related to the non-linear behavior of both MOSFET and Schottky Barrier Diodes (SBD) are discussed and figures of merit are introduced for their analysis. Influence of detector arrays geometric topology on their performances (Cutoff frequency, parasitic, Quality-factor, Sensitivity, Responsiveness, etc.) is studied based on careful experimental characterizations. Importance of proper Co-Design of Detector-Antenna system as a unified entity is underlined.

3-D Multilayer Copper Interconnects for High-Performance Monolithic Devices and Passives

This paper presents a new and efficient low-cost multilayer 3-D copper interconnect process for monolithic devices and passives. It relies on the BPN and SU-8 photoresists, associated with an optimized electroplating process to form multilevel 3-D interconnects in a single metallization step. The SU-8 is used as a permanent thick dielectric layer that is patterned underneath specific locations to create the desired 3-D interconnect shape. A 3-D seed layer is deposited above the SU-8 and the substrate to ensure 3-D electroplating current flow. The BPN is used as a thick mold for copper electroplating with an aspect ratio as high as 16:1. An optimized 3-D copper electroplating process is later used to grow 3-D interconnects, ensuring transition between all metallic layers. Finally, high-Q (55 at 5 GHz) power inductors are designed and integrated above a 50 W RF power laterally diffused metal oxide semiconductor device using this process.

A nanoparticule-based ferromagnetic dielectric Fe/Co composite for RF integrated inductors

A new ferromagnetic dielectric material formed from insulated Fe/Co nanoparticles is presented. This material is characterised using an original technique based on a silicon micromachined suspended CPW. Then, a spiral integrated RF inductor is designed which implements this material. Measurements demonstrate an up to 80% increase in the inductance value until 2 GHz, while the quality factor is improved until 1 GHz. These results confirm the high potentialities of this material for RF passive applications. Finally, because its dielectric nature, this material appears compatible with low cost microelectronic process.

Solenoidal transformers for magnetic materials integration

This paper presents the design, fabrication and characterization of suspended solenoidal transformers fabricated using a low cost single step 3D copper electroplating process. The design and optimization of solenoidal transformers with and without magnetic core are performed using HFSS. After optimization, the suspended structures reveal good electrical performance. The addition of a magnetic core to these structures shows a significant improvement of its electrical properties. Thus, an increase of 10% on Gmax, 20% on coupling coefficient k, 80% on the quality factor Q and 350% on the inductance is observed. Under probe measurements carried on the suspended structures without magnetic core exhibit a Gmax of -1.45 dB and a Q of 28.5 at 2.5 GHz. The enhanced performance coupled with the low cost 3D process makes these transformers excellent candidates for todays RF applications.

Accurate package model extraction up to 110 GHz using one-port measurements. Application to a 77 GHz radar transceiver

A methodology for an accurate modeling of a die-to-board transition using one-port measurements is presented in this paper. This methodology aims to build a valid model from DC to 110 GHz, applicable to any package transition and regardless of the technology used for the die. The package transition model is extracted using an Open-Short-Load (OSL) based algorithm and ElectroMagnetic simulations corrected from specific measurements. This methodology is used for the Fan-out Wafer-Level Package (WLP) modeling of an encapsulated 77 GHz automotive radar transceiver. The experimental characterization of this transceiver confirms the package model accuracy up to 110 GHz.

On-Wafer Measurement Errors Due to Unwanted Radiations on High-Q Inductors

This paper investigates the disagreements that may occur between on-wafer measurements and electromagnetic (EM) simulations of high-Q inductive devices. Such disagreements are highlighted on a planar spiral inductor and a 3-D solenoid which exhibit measured maximum Q-factors of 27 and 35, respectively, while 42 and 45 were expected from EM simulations. Both devices are fabricated on high-resistivity substrates. A radiative interaction is identified between RF probe and inductive device under test. By using EM simulations, extra-losses associated with this parasitic effect are fully modeled through the calculation of radiation and dissipation related Q-factors. Adjustments of on-wafer probe setup are proposed to reduce this parasitic effect. Finally, the 3-D solenoid inductor is characterized using a new experimental fixture, and the maximum Q of 45 predicted by EM simulation is retrieved.

Efficent low cost process for single step metal forming of 3D interconnected above-IC inductors

This paper presents a novel and efficient low cost process capable of integrating high-Q above-IC inductors and their interconnects using a single electroplating step. It relies on the SU8 and BPN resist as well as an optimized electroplating technique to form the 3D interconnected inductor. The SU8 is used to form a thick layer located underneath the inductor to elevate it from the substrate. Then, the BPN is used as a high resolution mold (16:1) for copper electroplating. Standard or time optimized electroplating is later used to grow copper in a 3D manner, making the transition between all metallic layers straight forward. High-Q (55 @ 5 GHz) power inductors have been designed and integrated above an RF power LDMOS device using this process. Finally, the process capabilities are demonstrated by integrating a solenoid inductor using only two lithography masks and a single electroplating step.