Ayman Alfalou

Simultaneous fusion, compression, and encryption of multiple images

We report a new spectral multiple image fusion analysis based on the discrete cosine transform (DCT) and a specific spectral filtering method. In order to decrease the size of the multiplexed file, we suggest a procedure of compression which is based on an adapted spectral quantization. Each frequency is encoded with an optimized number of bits according its importance and its position in the DC domain. This fusion and compression scheme constitutes a first level of encryption. A supplementary level of encryption is realized by making use of biometric information. We consider several implementations of this analysis by experimenting with sequences of gray scale images. To quantify the performance of our method we calculate the MSE (mean squared error) and the PSNR (peak signal to noise ratio). Our results consistently improve performances compared to the well-known JPEG image compression standard and provide a viable solution for simultaneous compression and encryption of multiple images.

Assessing the performance of a method of simultaneous compression and encryption of multiple images and its resistance against various attacks

We introduce a double optimization procedure for spectrally multiplexing multiple images. This technique is adapted from a recently proposed optical setup implementing the discrete cosine transformation (DCT). The new analysis technique is a combination of spectral fusion based on the properties of DCT, specific spectral filtering, and quantization of the remaining encoded frequencies using an optimal number of bits. Spectrally multiplexing multiple images defines a first level of encryption. A second level of encryption based on a real key image is used to reinforce encryption. A set of numerical simulations and a comparison with the well known JPEG (Joint Photographic Experts Group) image compression standard have been carried out to demonstrate the improved performances of this method. The focus here will differ from the method of simultaneous fusion, compression, and encryption of multiple images (SFCE) [Opt. Express 19, 24023 (2011)] in the following ways. Firstly, we shall be concerned with optimizing the compression rate by adapting the size of the spectral block to each target image and decreasing the number of bits required to encode each block. This size adaptation is achieved by means of the root-mean-square (RMS) time-frequency criterion. We found that this size adaptation provides a good tradeoff between bandwidth of spectral plane and number of reconstructed output images. Secondly, the encryption rate is improved by using a real biometric key and randomly changing the rotation angle of each block before spectral fusion. By using a real-valued key image we have been able to increase the compression rate of 50% over the original SFCE method. We provide numerical examples of the effects for size, rotation, and shifting of DCT-blocks which play noteworthy roles in the optimization of the bandwidth of the spectral plane. Inspection of the results for different types of attack demonstrates the robustness of our procedure.

A low-power, high-speed DCT architecture for image compression: Principle and implementation

We present a new design of low-power and high-speed Discrete Cosine Transform (DCT) for image compression to be implemented on Field Programmable Gate Arrays (FPGAs). The proposed compression method converts the image to be compressed in many lines of 8 pixels and then applies our optimized 1D-DCT algorithm for compression. The DCT optimization is based on the hardware simplification of the multipliers used to compute the DCT coefficients. In fact, by using constant multipliers based on Canonical Signed Digit (CSD) encoding, the number of of adders, subtracters and registers will be minimum. To further decrease the number of required arithmetic operators, a new technique based on Common Subexpression Elimination (CSE) is examined. FPGA implementations prove that the CSE implies less computations, less material complexity and a dynamic power saving of about 22% at 110 MHz of clock frequency in Spartan3E device.

Implementation techniques of high-order FFT into low-cost FPGA

In this paper, our objective is to detail know-how and techniques that can help the designer of electronic circuits to develop and to optimize their own IP in a reasonable time. For this reason, we propose to optimize existing FFT algorithms for low-cost FPGA implementations. For that, we have used short length structures to obtain higher length transforms. Indeed, we can obtain a VLSI structure by using log4 (N) 4-point FFTs to construct N-point FFT rather than (N/8) log8 (N) 8-point FFTs. Furthermore, two techniques are used to yield with VLSI architecture. Firstly, the radix-4 FFT is modified to process one sample per clock cycle. Secondly, the memory is shared and divided into 4 parts to reduce the consumed resources and to improve the overall latency. Comparisons with commercial IP cores show that the low area architecture presents the best compromise in terms of speed/area.

A VLSI implementation of a new simultaneous images compression and encryption method

In this manuscript, we describe a fully pipelined single chip architecture for implementing a new simultaneous image compression and encryption method suitable for real-time applications. The proposed method exploits the DCT properties to achieve the compression and the encryption simultaneously. First, to realize the compression, 8-point DCT applied to several images are done. Second, contrary to traditional compression algorithms, only some special points of DCT outputs are multiplexed. For the encryption process, a random number is generated and added to some specific DCT coefficients. On the other hand, to enhance the material implementation of the proposed method, a special attention is given to the DCT algorithm. In fact, a new way to realize the compression based on DCT algorithm and to reduce, at the same time, the material requirements of the compression process is presented. Simulation results show a compression ratio higher than 65% and a PSNR about 28 dB. The proposed architecture can be implemented in FPGA to yield a throughput of 206 MS/s which allows the processing of more than 30 frames per second for 1024×1024 images.

Fast face recognition approach using a graphical processing unit “GPU”

In this manuscript, we present an implementation of a correlation method for face recognition application on GPU. Our correlator is based on the famous “4f” setup and the use of a Phase Only Filter (POF). Traditionally, the correlation method is implemented using optical components for real-time application. Unfortunately, optical implementation is complex and has exorbitant price. To cope with these drawbacks and in order to benefit from the accuracy of the correlation method, we propose in this work to implement the correlation using GPU. To this end, we will take an interest in the mathematical aspect of the correlation method to identify the processing to be implemented on GPU. Simulations results about the implementation of the face recognition application on GPU showed the efficiency of our proposed design. Moreover, comparison between GPU and CPU in terms of execution time have been made and shows that, to identify one face among 4, GPU Nvidia Geforce 8400 GS is 3 times faster than the Intel Core 2 CPU 2.00 GHZ (using Matlab).

Optimized architecture using a novel subexpression elimination on loeffler algorithm for DCT-based image compression

The canonical signed digit (CSD) representation of constant coefficients is a unique signed data representation containing the fewest number of nonzero bits. Consequently, for constant multipliers, the number of additions and subtractions is minimized by CSD representation of constant coefficients. This technique is mainly used for finite impulse response (FIR) filter by reducing the number of partial products. In this paper, we use CSD with a novel common subexpression elimination (CSE) scheme on the optimal Loeffler algorithm for the computation of discrete cosine transform (DCT). To meet the challenges of low-power and high-speed processing, we present an optimized image compression scheme based on two-dimensional DCT. Finally, a novel and a simple reconfigurable quantization method combined with DCT computation is presented to effectively save the computational complexity. We present here a new DCT architecture based on the proposed technique. From the experimental results obtained from the FPGA prototype we find that the proposed design has several advantages in terms of power reduction, speed performance, and saving of silicon area along with PSNR improvement over the existing designs as well as the Xilinx core.

AREA-DELAY EFFICIENT FFT ARCHITECTURE USING PARALLEL PROCESSING AND NEW MEMORY SHARING TECHNIQUE

In this paper we present a novel architecture for FFT implementation on FPGA. The proposed architecture based on radix-4 algorithm presents the advantage of a higher throughput and low area-delay product. In fact, the novelty consists on using a memory sharing and dividing technique along with parallel-in parallel-out Processing Elements (PE). The proposed architecture can perform N-point FFT using only 4/3N delay elements and involves a latency of N/4 cycles. Comparison in terms of hardware complexity and area-delay product with recent works presented in the literature and commercial IPs has been made to show the efficiency of the proposed design. Moreover, from the experimental results obtained from a FPGA prototype we find that the proposed design involves an execution time of 56% lower than that obtained with Xilinx IP core and an increase of 19% in the throughput by area ratio for 256-point FFT.

Joint Optimization of Low-Power DCT Architecture and Efficient Quantization Technique for Embedded Image Compression

The Discrete Cosine Transform (DCT)-based image compression is widely used in today’s communication systems. Significant research devoted to this domain has demonstrated that the optical compression methods can offer a higher speed but suffer from bad image quality and a growing complexity. To meet the challenges of higher image quality and high speed processing, in this chapter, we present a joint system for DCT-based image compression by combining a VLSI architecture of the DCT algorithm and an efficient quantization technique. Our approach is, firstly, based on a new granularity method in order to take advantage of the adjacent pixel correlation of the input blocks and to improve the visual quality of the reconstructed image. Second, a new architecture based on the Canonical Signed Digit and a novel Common Subexpression Elimination technique is proposed to replace the constant multipliers. Finally, a reconfigurable quantization method is presented to effectively save the computational complexity. Experimental results obtained with a prototype based on FPGA implementation and comparisons with existing works corroborate the validity of the proposed optimizations in terms of power reduction, speed increase, silicon area saving and PSNR improvement.