Ayman Elnaggar

A Call Admission Control Protocol for Multimedia Cellular Networks

The performance of any cellular wireless network, as well as its revenue (number of customers using the network, and their degree of satisfaction) is determined to a great extent by its call admission control (CAC) protocol. As its name implies, the CAC determine if a new call request is granted, or rejected. In this paper, we propose a call admission control protocol for cellular multimedia wireless networks. Multimedia networks are characterized by a wide variety of bandwidth requests, priorities, and drop-off/rejection requirements by different customers. Our protocol depends on degrading the existing calls, according to their degradation priority, by reducing the bandwidth allocated to them in order to admit new calls according to their admission priority. Our protocol is too complicated for an analytical solution. However we present a Markov Model of a simplified version of our protocol for completeness, a Markov representation of the protocol is too complicated to be of any real value. Extensive simulation results show how our proposed protocol can improve the drop-off/rejection ratio for large bandwidth calls and at the same time maintain the quality of service requested by important calls.

A new tensor product formulation for Toom's convolution algorithm

This correspondence presents a new recursive formulation of Tooms algorithm that allows the generation of higher order (longer size) one-dimensional (1-D) convolution architectures from three lower order (shorter sizes) convolution architectures. Our methodology is based on manipulating tensor product forms so that they can be mapped directly into modular parallel architectures. The resulting convolution circuits have very simple modular structure and regular topology.

A modified shuffle-free architecture for linear convolution

This paper presents a class of modified parallel very large scale integration architectures for linear convolution in shuffle-free forms. The proposed algorithms show that for 1-D convolution, the number of lower-order convolutions can be reduced from three to two allowing a hardware saving without slowing down the processing speed. The proposed partitioning strategy results in a core of data-independent convolution computations. Such computations can be overlapped in software pipelines, super pipelines, or executed concurrently on multiple functional units in a DSP chip.

An efficient architecture for multi-dimensional convolution

This paper presents modified parallel architectures for multidimensional (m-d) convolution. We show that for two-dimensional (2-d) convolutions, with careful design, the number of lower-order 2-d convolutions can be reduced from nine to six with a computation saving of 33%. However, the original speed of the computations is not affected. The proposed partitioning strategy results in a core of data-independent convolution computations, and can be generalized to the m-d convolution. The resulting very large scale integration networks have very simple modular structure, highly regular topology, and use simple arithmetic devices.

A new recursive algorithm for multidimensional convolution

This paper presents a novel recursive algorithm for generating higher order m-dimensional (m-D) convolution by combining the computation of 3/sup m/ identical lower order (smaller size) convolution computations, and its implementation in parallel VLSI networks. The resulting VLSI architectures have very simple modular structure, highly regular topology, and use simple arithmetic units. Additionally, the proposed architectures have very small depth and contain only a single stage of multipliers, while all other stages contain adders only.

A new recursive formulation for 2-D WHT

This paper presents a new recursive formulation for computing the Walsh-Hadamard Transform (WHT) that allows the generation of higher order (longer size) 2-D WHT architectures from four lower order (shorter sizes) WHT architectures. Our methodology is based on manipulating tensor product forms so that they can be mapped directly into modular parallel architectures. The resulting WHT circuits have very simple modular structure and regular topology.

A Unified Framework for Mapping Multidimensional Separable DSP Transforms onto parallel VLSI Structures

This paper presents a general approach for separable DSP transforms that allows the generation of higher order (longer size) multidimensional (m-d) architectures from 2m lower order (shorter sizes) architectures. The objective of our work is to derive a unified framework and a design methodology that allows direct mapping of the proposed algorithms into modular VLSI architectures. Our methodology is based on manipulating tensor product forms so that they can be mapped directly into modular parallel architectures. The resulting circuits have very simple modular structure and regular topology.

An improved Toom's algorithm for linear convolution

This article presents an improved Tooms algorithm that allows hardware savings without slowing down the processing speed. We derive formulae for the number of multiplications and additions required to compute the linear convolution of size n = 2/sup /spl alpha//. We demonstrate the computational advantage of the proposed improved algorithm when compared to previous algorithms, such as the original matrix-vector multiplication and the FFT algorithms.

An efficient algorithm for multidimensional convolution

This paper presents a novel recursive algorithm for generating higher-order multidimensional (or m-D for short) convolution by combining the computation of 3/sup m/ identical lower-order (smaller size) convolution computations, and its implementation in parallel VLSI networks. We show that for 2-D convolutions, with careful design, the number of lower-order 2-D convolutions can be reduced from nine to six with a computation saving of 35%. The resulting VLSI architectures have very simple modular structure, highly regular topology, and use simple arithmetic units.