Mokhtar Aboelaze

Current and future trends in sensor networks: a survey

Sensor networks consist of a large number of very small nodes that are deployed in some geographical area. The purpose of the network is to sense the environment and report what happens in the area it is deployed in. Sensor networks are used in many applications. In military applications they are used for surveillance and target tracking. In industrial applications, sensor networks are used in monitoring hazardous chemicals. They are also used in monitoring the environment and in early fire warning in forests as well as seismic data collections. Sensor networks face new challenges not known in cellular and ad-hoc wireless networks. In this paper, we report on currents and new trends in sensor networks. We also present some of the challenges and future work in sensor networks.

A call admission protocol for cellular networks that supports differentiated fairness

Call admission protocols play a central role in determining the performance of any network. The call admission protocol must decide either to accept a call or reject it; at the same time, it must deal with different classes of calls that have different bandwidth and quality of service (QoS) requirements, and different priorities. It must also maintain some form of fairness (depending on QoS) and maintain a reasonable utilization of the channel. We assume a cellular system and we present a new call admission protocol. Our protocol is simple to implement, and it can support differentiated fairness in call acceptance. We also present a Markov chain representation of a system using our proposed protocol. Finally, we present simulation results in order to compare our protocol to previous protocols and show that our protocol can achieve the required differentiated fairness without sacrificing channel utilization.

Systematic designs of buffers in macropipelines of systolic arrays

This special issue is devoted to applications whose unstructured characteristics make finding efficient implementations on supercomputers more difficult. In effect, in order to achieve high performance in problem-solving in parallel, efficiency issues like data layout, data dependencies, locality, work load, load balance, and minimization of communications must be carefully assessed. In special cases, when the problem at hand presents a structure regular enough to be dealt with automatically, it is sufficient to leave the parallelization and optimization to existing tools. However, most of the important applications (e.g., image processing, combinatorial optimization, and sparse matrix computations) show structures that lack regularity; consequently, performance enhancement by exploitation of parallelism requires new design techniques (e.g., approximation, randomization, and new programming models) and tools (e.g., compilers, partitioners, and schedulers) for such problems. Therefore, due to the challenges and the many research issues involved, the state-of-the-art in this field is rapidly advancing. The primary goal of this special issue is thus to report on the forefront of irregular problems in supercomputing applications and to identify future directions for research in the area. All of the papers published in this issue were thoroughly refereed by at least three reviewers, and were revised accordingly in order to meet the Journal of Parallel and Distributed Computing ’s high standards. We have classified these eight papers (out of the 51 submitted) into the three categories mentioned above, as follows:

Routing in Optical and Non-Optical Networks using Boolean Satisfiability

Today, most routing problems are solved using Dijkstra’s shortest path algorithm. Many efficient implementations of Dijkstra’s algorithm exist and can handle large networks in short runtimes. Despite these advances, it is difficult to incorporate user-specific conditions on the solution when using Dijkstra’s algorithm. Such conditions can include forcing the path to go through a specific node, forcing the path to avoid a specific node, using any combination of inclusion/exclusion of nodes in the path, etc. In this paper, we propose a new approach to solving the shortest path problem using advanced Boolean satisfiability (SAT) techniques. SAT has been heavily researched in the last few years. Significant advances have been proposed and has lead to the development of powerful SAT solvers that can handle very large problems. SAT solvers use intelligent search algorithms that can traverse the search space and efficiently prune parts that contain no solutions. These solvers have recently been used to solve many problems in Engineering and Computer Science. In this paper, we show how to formulate the shortest path problem in non-optical networks as a SAT problem. We also show how to use SAT in finding routing and wavelength assignments in optical networks. Our approach is verified on various network topologies. The results are promising and indicate that using the proposed approach can improve on previous techniques.

A Call Admission Control Protocol for Multimedia Cellular Networks

The performance of any cellular wireless network, as well as its revenue (number of customers using the network, and their degree of satisfaction) is determined to a great extent by its call admission control (CAC) protocol. As its name implies, the CAC determine if a new call request is granted, or rejected. In this paper, we propose a call admission control protocol for cellular multimedia wireless networks. Multimedia networks are characterized by a wide variety of bandwidth requests, priorities, and drop-off/rejection requirements by different customers. Our protocol depends on degrading the existing calls, according to their degradation priority, by reducing the bandwidth allocated to them in order to admit new calls according to their admission priority. Our protocol is too complicated for an analytical solution. However we present a Markov Model of a simplified version of our protocol for completeness, a Markov representation of the protocol is too complicated to be of any real value. Extensive simulation results show how our proposed protocol can improve the drop-off/rejection ratio for large bandwidth calls and at the same time maintain the quality of service requested by important calls.

Modified Hotspot Cache Architecture: A Low Energy Fast Cache for Embedded Processors

The cache memory plays a crucial role in the performance of any processor. The cache memory (SRAM), especially the on chip cache, is 3-4 times faster than the main memory (DRAM). It can vastly improve the processor performance and speed. Also the cache consumes much less energy than the main memory. That leads to a huge power saving which is very important for embedded applications. In todays processors, although the cache memory reduces the energy consumption of the processor, however the energy consumption in the on-chip cache account to almost 40% of the total energy consumption of the processor. In this paper, we propose a cache architecture, for the instruction cache, that is a modification of the hotspot architecture. Our proposed architecture consists of a small filter cache in parallel with the hotspot cache, between the L1 cache and the main memory. The small filter cache is to hold the code that was not captured by the hotspot cache. We also propose a prediction mechanism to steer the memory access to either the hotspot cache, the filter cache, or the L1 cache. Our design has both a faster access time and less energy consumption compared to both the filter cache and the hotspot cache architectures. We use Mibench and Mediabench benchmarks, together with the simplescalar simulator in order to evaluate the performance of our proposed architecture and compares it with the filter cache and the hotspot cache architectures. The simulation results show that our design outperforms both the filter cache and the hotspot cache in both the average memory access time and the energy consumption

Energy efficient i-cache using multiple line buffers with prediction

Modern microprocessors dedicate a large portion of the chip area to the cache. Decreasing the energy consumption of the microprocessor, which is a very important design goal especially for small, battery powered, devices, depends on decreasing the energy consumption of the memory/cache system in the microprocessor. The authors investigate the energy consumption in caches and present a novel cache architecture for reduced energy instruction caches. Our cache architecture consists of the L1 cache, multiple line buffers and a prediction mechanism to predict which line buffer, or L1 cache, to access next. In the proposed technique, the authors use the multiple line buffers as a continuous small filter cache that can catch most of the cache access but they access only a single line buffer, thus reducing the energy consumption of the cache. They used simulation to evaluate the proposed architecture and to compare it with the HotSpot cache, filter cache and single line buffer cache. Simulation results show that the approach is slightly faster than the above mentioned caches, and it consumes considerably less energy than any of these cache architectures.

A modified shuffle-free architecture for linear convolution

This paper presents a class of modified parallel very large scale integration architectures for linear convolution in shuffle-free forms. The proposed algorithms show that for 1-D convolution, the number of lower-order convolutions can be reduced from three to two allowing a hardware saving without slowing down the processing speed. The proposed partitioning strategy results in a core of data-independent convolution computations. Such computations can be overlapped in software pipelines, super pipelines, or executed concurrently on multiple functional units in a DSP chip.

Identifying the Shortest Path in Large Networks using Boolean Satisfiability

Today, most routing problems are solved using Dijkstras shortest path algorithm. Many efficient implementations of Dijkstras algorithm exist and can handle large networks in short runtimes. Despite these advances, it is difficult to incorporate user-specific conditions on the solution when using Dijkstras algorithm. Such conditions can include forcing the path to go through a specific node, forcing the path to avoid a specific node, using any combination of inclusion/exclusion of nodes in the path, etc. In this paper, we propose a new approach to solving the shortest path problem using advanced Boolean satisfiability (SAT) techniques. SAT has been heavily researched in the last few years. Significant advances have been proposed and has lead to the development of powerful SAT solvers that can handle very large problems. SAT solvers use intelligent search algorithms that can traverse the search space and efficiently prune parts that contain no solutions. These solvers have recently been used to solve many problems in engineering and computer science. In this paper, we show how to formulate the shortest path problem as a SAT problem. Our approach is verified on various network topologies. The results are promising and indicate that using the proposed approach can improve on previous techniques

An efficient architecture for multi-dimensional convolution

This paper presents modified parallel architectures for multidimensional (m-d) convolution. We show that for two-dimensional (2-d) convolutions, with careful design, the number of lower-order 2-d convolutions can be reduced from nine to six with a computation saving of 33%. However, the original speed of the computations is not affected. The proposed partitioning strategy results in a core of data-independent convolution computations, and can be generalized to the m-d convolution. The resulting very large scale integration networks have very simple modular structure, highly regular topology, and use simple arithmetic devices.