Azadeh Safari

Simulation and Hardware Implementation of Incremental Conductance MPPT With Direct Control Method Using Cuk Converter

This paper presents simulation and hardware implementation of incremental conductance (IncCond) maximum power point tracking (MPPT) used in solar array power systems with direct control method. The main difference of the proposed system to existing MPPT systems includes elimination of the proportional-integral control loop and investigation of the effect of simplifying the control circuit. Contributions are made in several aspects of the whole system, including converter design, system simulation, controller programming, and experimental setup. The resultant system is capable of tracking MPPs accurately and rapidly without steady-state oscillation, and also, its dynamic performance is satisfactory. The IncCond algorithm is used to track MPPs because it performs precise control under rapidly changing atmospheric conditions. MATLAB and Simulink were employed for simulation studies, and Code Composer Studio v3.1 was used to program a TMS320F2812 digital signal processor. The proposed system was developed and tested successfully on a photovoltaic solar panel in the laboratory. Experimental results indicate the feasibility and improved functionality of the system.

Incremental conductance MPPT method for PV systems

This paper presents incremental conductance method for maximum power point tracking (MPPT) using DC-DC cuk converter. Comprehensive analysis and simulation of KC85T solar module and equivalent electric circuit are provided while effects of various environmental conditions on the PV module behavior is investigated. In order to fully understand the PV module working specifications fundamental characteristics of PV cells are discussed. Block diagram model of a PV module was developed in Simulink for plotting the curves. KC85T solar module is used in simulations and results indicate speed and accuracy of the proposed system.

Simple and low cost incremental conductance maximum power point tracking using buck-boost converter

Cost of the photovoltaic (PV) systems and their peripherals has been always an issue when considering them for various applications. Using an inexpensive maximum power point tracking (MPPT) system is a simple but efficient solution to reduce the cost of the PV systems and increase the public acceptance. This paper presents the simulation and hardware implementation of incremental conductance algorithm using buck-boost converter and PIC18F4520 controller. Design and simulation of the proposed system are presented using matlab and simulink tools. The proposed system is also tested on KC85T PV module for constant and changing weather conditions. Experimental results indicated the capability and functionality of the proposed system on tracking maximum power point with the voltage ripple ratio = 0.006, which is near to the ideal mathematically calculated assessment. The proposed MPPT system helps to reduce the complexity and cost of the PV systems and also ensures the largest operating region of the PV module.

Implementation of incremental conductance method with direct control

This paper presents incremental conductance (IncCond) MPPT using direct control method in which duty cycle is adjusted inside the algorithm thus need for use another control loop is eliminated while tracking is done perfectly. The steady state oscillations are reduced and dynamic performance is improved. Design and theoretical study and analysis of the proposed system are provided and its feasibility is investigated in Matlab/Simulink simulations. Eventually results are submitted to evaluate the closed loop system.

Power-performance enhancement of two-dimensional RNS-based DWT image processor using static voltage scaling

Digital image processing is widely used in fast and high-performance applications. The high speed and functional requirements of such applications, however, lead to increased power consumption. Hence, finding a way to solve the power-performance issues is of great importance. In this paper, we present the power-performance enhancement of a two-dimensional (2D) discrete wavelet transform (DWT) image processor using the residue number system (RNS) and the static voltage scaling (SVS) scheme. The aim of this paper is to investigate the effects of the RNS and SVS scheme on the proposed image processor. The original contributions of the proposed design include a low-complexity hardware architecture of the RNS-based filter banks, optimized transposition units and exploiting the SVS scheme to reduce the power consumption. The multiplierless scheme of the RNS-based filter banks and the binary-coded number format are used to save on hardware complexity, while modular arithmetics and 6-bit dyadic fraction filter coefficients are applied to improve the system performance. The bi-orthogonal discrete wavelet transform CDF97 is chosen to compress the images due to its multi-resolution features and its ability to localize finite signals. The proposed design has been synthesized using the generic library SAED 90 nmEDK with the Synopsys Design Compiler (DC).

Performance comparison of orthogonal and biorthogonal wavelets using technology libraries

Wavelets are powerful tools that can be used in signal processing and data compression. They are an excellent alternative to Fourier transforms for applications with transient input signals. There is a large volume of published studies describing the use of wavelets in various fields. However, properties of each family for designs with technology libraries have never been investigated. The present work aims to study the most commonly used wavelets (orthogonal and biorthogonal) and compare the area, speed and power consumption of each family when the designs are synthesized using 150 nm standard cell TSMC library. The aim of this paper is to serve as a convenient reference for wavelet users and reviews.

ASIC design in Residue Number System for calculating minimum sum of Absolute Differences

The Sum of Absolute Differences (SAD) is widely used in motion-estimation algorithms, the most computationally intensive task in video compression, and also in determining similarities between two data sets. This paper proposes a SAD hardware implementation using a Residue Number System (RNS). Residue Number Systems have been used for decades in designing low-power and high-speed computer hardware, because of their inherent parallel structure. In RNS, large integers are represented as sets of smaller integers or residues, where the number bases or moduli are mutually prime. Since these residues are independent from each other, mathematical operations such as addition, subtraction and multiplication can be carried out without any carry propagation between residues, which is in most cases a limiting factor in binary systems. However, some arithmetical operations such as comparison and division are more difficult in RNS than in conventional binary systems, such as determining the sign and magnitude comparison of two numbers. The proposed SAD architecture is based on a very recent advance in fast sign-detection algorithms for RNS, and the experimental results show that the proposed architecture has higher speed and less area than previous SAD implementations.

Novel implementation of full adder based scaling in Residue Number Systems

The need for faster digital circuitry has turned the researchers to alternative number systems and arithmetic level modifications. One such number system being used is the Residue Number System (RNS). With computationally fast addition, subtraction and multiplication it has become widely used in many vast areas of Digital Signal Processing (DSP). The drawback to using RNS is that it has several computationally slow and resource intense operations, most notably, scaling and conversion. This paper presents a novel implementation of three moduli set {2n - 1, 2n, 2n + 1} scaling system and the constant scaling factor. The main difference of the proposed system to existing scaling systems includes elimination of the overhead conversion system and employing modular reducers in implementation of the design. Many algorithms for fast scaling in RNS exist, but this paper will focus on developing a particular algorithm using adder based techniques.

The Application of Lifting DWT in Digital Image Processing

Discrete wavelet transform (DWT) has shown great performance in digital image compression and denoising applications. It has been the transformation used for source encoding in JPEG2000 still image compression standard and FBI wavelet scalar quantization. This paper has adopted the lifting DWT which is the most computation-efficient scheme of wavelet analysis and outlines the multi-resolution features of the wavelet transform. Details of the lifting wavelet transform are analyzed to propose a high-speed, less-area and power-efficient digital image compression scheme. Maple 15 has been employed for design and simulation studies.

Four tap Daubechies filter banks based on RNS

Discrete wavelet transform (DWT) has shown great performance in digital image compression and denoising applications. It is the transformation used for source encoding in JPEG2000 still image compression standard and FBI wavelet scalar quantization. DWT is capable of fast image compression at less area and low power consumption. This paper presents 4-tap orthogonal DWT based on the residue number system. Hardware complexity reduction and design improvement are achieved by employing RNS for arithmetic operations and LUT sharing between low pass and high pass filters. The RNS based DWT is simulated and implemented on the Xilinx FPGA to verify the functionality and efficiency of the design.