Azam Beg

Enabling sizing for enhancing the static noise margins

This paper suggests a transistor sizing method for classical CMOS gates implemented in advanced technology nodes and operating at low voltages. The method relies on upsizing the length (L) of all transistors uniformly, and balancing the voltage transfer curves (VTCs) for maximizing the static noise margins (SNMs). We use the most well-known CMOS gates (INV, NAND-2, NOR-2) for introducing the novel sizing method, as well as for validating the concept and evaluating its performances. The results show that sizing has not entirely exhausted its potential, allowing to go beyond the well established delay-power tradeoff, as sizing can increase SNMs by: (i) adjusting the threshold voltages (VTH) and their variations (σVTH); and (ii) balancing the VTCs. Simulation results show that this sizing method enables more reliable (i.e., noise-robust and variation-tolerant) CMOS gates, which could operate correctly at very low supply voltages, hence leading to ultra-low voltage/power circuits.

GREDA: A Fast and More Accurate Gate Reliability EDA Tool

Generic as well as customized reliability electronic design automation (EDA) tools have been proposed in the literature and used to estimate the reliability of both present and future (nano)circuits. However, the accuracy of many of these EDA tools is questionable as they: 1) either assume that all gates have the same constant probability of failure (PFGATE=const.) , or 2) use very simple approaches to estimate the reliability of the elementary gates. In this paper, we introduce a gate reliability EDA tool (GREDA) that is able to estimate more accurately the reliability of CMOS gates by considering: 1) the gates topology; 2) the variable probability of failure of the individual devices (PFDEV); 3) the applied input vector; 4) the reliability of the input signals; and 5) the input voltage variations (which can be linked to the allowed noise margins). GREDA can be used to calculate PFGATE due to different types of faults and/or defects, and to estimate the effects of enhancing PFDEV on PFGATE. Simulation results show that GREDA can improve on the accuracy of reliability calculations at the gate level.

Atto-Joule gates for the whole voltage range

Reducing the supply voltage is by far the most widely used low-power technique, as reducing dynamic power quadratically and leakage power linearly, while sacrificing on performances. A similar but less explored route is to reduce and/or limit currents (instead of reducing voltages), e.g., through transistor sizing. This paper details a comparison of a reverse-sized CMOS scheme (which reduces currents), with both a classical CMOS implementation and an ultra low power (ULP) sub-threshold CMOS scheme. Simulation results show that the reverse-sized CMOS inverter performs well over the whole range of supply voltages: (i) it dissipates significantly less than a classical CMOS inverter (20–60×), while it does degrade performances (5–20×) but less than power gaining, i.e., not proportionally; (ii) it is much faster (100–200×) than a ULP inverter, at moderately larger power consumptions (10–40×), but again less than proportional; and (iii) its power-delay-product (PDP) is constantly 5–8× lower than that of the other two inverters considered over the whole range of supply voltages. In particular, a reverse-sized CMOS inverter in 16nm at 300mV has a delay of 9.16ns while breaking the atto-Joule barrier (0.906aJ).

Highly reliable and low-power full adder cell

Full adders (FAs) are essential for digital circuits including microprocessors, digital signal processors, and microcontrollers. Both the power consumption and the reliability of FAs are crucial as they directly affect: arithmetic logic units, floating-point units, as well as memory address calculations. This paper studies the effect threshold voltage (VTH) variations play on the reliability of a classical 28-transistor FA, and shows that reliability can be enhanced without increasing the occupied area, and while also reducing power consumption. An enabling transistor sizing scheme is used to improve on reliability without increasing power consumption (as reducing and limiting currents). The proposed FA in 16nm predictive technology model (PTM) is significantly more reliable (six orders of magnitude in case of Cout, and three orders of magnitude in case of Sum at 10% input variations) and dissipates 38× less than a classical FA, while being 6× slower.

Optimum Reliability Sizing for Complementary Metal Oxide Semiconductor Gates

Introducing redundancy at the device-level has been proposed as the most effective way to improve reliability. With the remarkable reliability of the complementary metal oxide semiconductor (CMOS) transistors the semiconductor industry was able to fabricate, the research on device-level redundancy has reduced. However, the increasing sensitivity to noise and variations (due to the massive scaling) of the CMOS transistors has led to a revival of interest in device-level redundancy schemes during the last decade. In this paper, we introduce a novel transistor sizing method that can be used to significantly reduce the probability of failure of CMOS gates due to threshold voltage variations. The method has almost no impact on the occupied area. For a given reliability target, the proposed sizing method provides very large scale integration (VLSI) designers with several transistor sizing options which allow them to optimize the trade-off between reliability and the traditional power-area-delay design parameters. The simulation results reported in this paper will show that the proposed transistor sizing method can improve the reliabilities of classical INV, NAND-2, and NOR-2 CMOS gates by factors of more than 105, 10, and 1010 respectively, while the area is increased by less than 50%.

Applicability of feed-forward and recurrent neural networks to Boolean function complexity modeling

In this paper, we present the feed-forward neural network (FFNN) and recurrent neural network (RNN) models for predicting Boolean function complexity (BFC). In order to acquire the training data for the neural networks (NNs), we conducted experiments for a large number of randomly generated single output Boolean functions (BFs) and derived the simulated graphs for number of min-terms against the BFC for different number of variables. For NN model (NNM) development, we looked at three data transformation techniques for pre-processing the NN-training and validation data. The trained NNMs are used for complexity estimation for the Boolean logic expressions with a given number of variables and sum of products (SOP) terms. Both FFNNs and RNNs were evaluated against the ISCAS benchmark results. Our FFNNs and RNNs were able to predict the BFC with correlations of 0.811 and 0.629 with the benchmark results, respectively.

Predicting processor performance with a machine learnt model

Architectural simulators are traditionally used to study the design trade-offs for processor systems. The simulators are implemented in a high-level programming language or a hardware descriptive language, and are used to estimate the system performance prior to the hardware implementation. The simulations, however, may need to run for long periods of time for even a small set of design variations. In this paper, we propose a machine learnt (neural network/NN) model for estimating the execution performance of a superscalar processor. Multiple runs for the model are finished in less than a few milliseconds as compared to days or weeks required for simulation-based methods. The model is able to predict the execution throughput of a processor system with over 85% accuracy when tested with six SPEC2000 CPU integer benchmarks. The proposed model has possible applications in computer architecture research and teaching.

Binary Decision Diagrams and neural networks

Abstract This paper describes a neural network approach that gives an estimation method for the space complexity of Binary Decision Diagrams (BDDs). A model has been developed to predict the complexity of digital circuits. The formal core of the developed neural network model (NNM) is a unique matrix for the complexity estimation over a set of BDDs derived from Boolean logic expressions with a given number of variables and Sum of Products (SOP) terms. Experimental results show good correlation between the theoretical results and those predicted by the NNM, which will give insights to the complexity of Very Large Scale Integration (VLSI)/Computer Aided Design (CAD) designs. The proposed model is capable of predicting the maximum BDD complexity (MaxBC) and the number of product terms (NPT) in the Boolean function that corresponds to the minimum BDD complexity (MinBC). This model provides an alternative way to predict the complexity of digital VLSI circuits.

Modelling the XOR/XNOR Boolean Functions Complexity Using Neural Network

This paper propose a model for the complexity of Boolean functions with only XOR/XNOR min-terms using back propagation neural networks (BPNNs) applied to binary decision diagrams (BDDs). The developed BPNN model (BPNNM) is obtained through the training process of experimental data using Brain Maker software package. The outcome of this model is a unique matrix for the complexity estimation over a set of BDDs derived from randomly generated Boolean expressions with a given number of variables and XOR/XNOR min-terms. The comparison results of the experimental and back propagation neural networks mode (BPNNM) underline the efficiency of this approach, which is capable of providing some useful clues about the complexity of the final circuit implementation.

Using simulators for teaching computer organization and architecture

An important problem in teaching the subjects of Computer Architecture and Organization (CO&CA) is the linking of the theoretical knowledge with the practical experience. Visualization of different computer hardware architectures with the use of the simulators enhances the learning process among students. Many useful computer simulators can help address this issue by covering various aspects of CO&CA. The programs range from simple simulators to specific teaching tools to advanced and specialized software. We assessed several simulators and selected one that was freely available and that enabled the students to learn the concepts to the fullest. This paper describes our experience of incorporating simulation tools into teaching the CO&CA to information technology and computing students. We demonstrate that the use of simulators helped students understand better how a computer was constructed and how it functioned internally.