Azita Emami

A Fully Intraocular High-Density Self-Calibrating Epiretinal Prosthesis

This paper presents a fully intraocular self-calibrating epiretinal prosthesis with 512 independent channels in 65 nm CMOS. A novel digital calibration technique matches the biphasic currents of each channel independently while the calibration circuitry is shared among every 4 channels. Dual-band telemetry for power and data with on-chip rectifier and clock recovery reduces the number of off-chip components. The rectifier utilizes unidirectional switches to prevent reverse conduction loss in the power transistors and achieves an efficiency > 80%. The data telemetry implements a phase-shift keying (PSK) modulation scheme and supports data rates up to 20 Mb/s. The system occupies an area of 4.5 ×3.1 mm2. It features a pixel size of 0.0169 mm2 and arbitrary waveform generation per channel. In vitro measurements performed on a Pt/Ir concentric bipolar electrode in phosphate buffered saline (PBS) are presented. A statistical measurement over 40 channels from 5 different chips shows a current mismatch with μ = 1.12 μA and σ = 0.53 μA. The chip is integrated with flexible MEMS origami coils and parylene substrate to provide a fully intraocular implant.

A 25 Gb/s 3D-Integrated CMOS/Silicon-Photonic Receiver for Low-Power High-Sensitivity Optical Communication

Integrating optical receivers based on double-sampling architecture exhibit a low-power alternative to those designed around transimpedance amplifiers (TIA). In this paper, we present a 3D-integrated CMOS/silicon-photonic optical receiver. The receiver features a low-bandwidth TIA integrating front-end double-sampling technique and dynamic offset modulation. The copper-pillar-based 3D-integration technology used here enables ultralow parasitics and 40 μm pitch for interconnection. We study different tradeoffs in designing an optical receiver and how to choose between a full-bandwidth TIA front-end and integrating architecture using a resistive front-end or a low-bandwidth TIA front-end. The design methodology is supported by measurements of two 3D-integrated prototypes based on a conventional TIA and a double-sampling integrating receiver. The proposed receiver architecture achieves -14.9 dBm of sensitivity and energy efficiency of 170 fJ/b at 25 Gb/s, while the conventional receiver achieves a sensitivity of -10.4 dBm and energy efficiency of 260 fJ/b at 21.2 Gb/s.

A 25Gb/s 170μW/Gb/s optical receiver in 28nm CMOS for chip-to-chip optical communication

A low-power high-speed optical receiver in 28nm CMOS is presented. The design features a novel architecture combining a low-bandwidth TIA front-end, double-sampling technique and dynamic offset modulation. The low-bandwidth TIA increases receivers sensitivity while adding minimal power overhead. Functionality of the receiver was validated and the design is compared with a conventional 3-stage TIA receiver via actual measurements. The proposed receiver architecture achieves error-free operation (BER<;10-12) at 25Gb/s with energy efficiency of 170fJ/b while the conventional receiver achieves error-free operation at 17.1Gb/s with energy efficiency of 260fJ/b.

22.3 A 4-to-11GHz injection-locked quarter-rate clocking for an adaptive 153fJ/b optical receiver in 28nm FDSOI CMOS

Modern SoC systems impose stringent requirements on on-chip clock generation and distribution. Ring-oscillator (RO) based injection-locked (IL) clocking has been used in the past to provide a low-power, low-area and low-jitter solution. Ring-based injection-locked oscillators (ILO) can also be used to generate quadrature phases from a reference clock without frequency division, which is desirable for half-rate and quarter-rate CDR. However, ILO inherently has a small locking range making it less suitable for wideband applications. In addition, drift in the free-running frequency due to PVT variations may lead to poor jitter performance and locking failures. Adding a PLL to an ILO provides frequency tracking. However, PLL-aided techniques have second-order characteristics that lead to jitter peaking. They also add design complexity and power consumption . We present a frequency-tracking method that exploits the dynamics of IL in a quadrature RO to increase the effective locking range. This quadrature locked loop (QLL) is used to generate accurate clock phases for a 4-channel optical receiver using a forwarded clock at quarter-rate. The QLL drives an ILO at each channel without any repeaters for local quadrature clock generation. Each local ILO has deskew capability for phase alignment. The receiver maintains per-bit energy consumption across wide data-rates (16 to 32Gb/s) by adaptive body biasing (BB) in a 28nm FDSOI technology.

A Modelling and Nonlinear Equalization Technique for a 20 Gb/s 0.77 pJ/b VCSEL Transmitter in 32 nm SOI CMOS

This paper describes an ultralow-power VCSEL transmitter in 32 nm SOI CMOS. To increase its power efficiency, the VCSEL is driven at a low bias current. Driving the VCSEL in this condition increases its inherent nonlinearity. Conventional pre-emphasis techniques cannot compensate for this effect because they have a linear response. To overcome this limitation, a nonlinear equalization scheme is proposed. A dynamic VCSEL modelling technique is used to generate the time-domain optical responses for “one” and “zero” bits. Based on the asymmetry of the two responses, the rising and falling edges are equalized separately. Additionally, instead of using fixed bit delays, the equalization delay is selected based on the bias current of the VCSEL. The efficiency of the proposed modelling and equalization technique is evaluated through simulations and measurements. The transmitter achieves energy efficiency of 0.77 pJ/b at 20 Gb/s and occupies 100 μm × 60 μm active silicon area.

A Wideband Injection-Locking Scheme and Quadrature Phase Generation in 65-nm CMOS

A novel technique for wideband injection locking in an LC oscillator is proposed. Phased-lock-loop and injection-locking elements are combined symbiotically to achieve wide locking range while retaining the simplicity of the latter. This method does not require a phase frequency detector or a loop filter to achieve phase lock. A mathematical analysis of the system is presented and the expression for new locking range is derived. A locking range of 13.4-17.2 GHz and an average jitter tracking bandwidth of up to 400 MHz were measured in a high- Q LC oscillator. This architecture is used to generate quadrature phases from a single clock without any frequency division. It also provides high-frequency jitter filtering while retaining the low-frequency correlated jitter essential for forwarded clock receivers.

A Wideband Injection Locked Quadrature Clock Generation and Distribution Technique for an Energy-Proportional 16–32 Gb/s Optical Receiver in 28 nm FDSOI CMOS

We present a novel frequency tracking method that exploits the dynamics of injection locking in a quadrature ring oscillator to increase the effective locking range from 5% (7-7.4 GHz) to 90% (4-11 GHz). The quadrature phase error between I and Q phases of an injection locked ring oscillator is derived and shown to contain frequency error information, both inside and outside the locking range. This error is utilized to form a first-order frequency tracking quadrature locked loop (QLL). This loop generates accurate clock phases for a 4-channel parallel optical receiver using a forwarded clock at quarter-rate. The QLL drives an ILO at each channel without any repeaters for local quadrature clock generation. Each local ILO has deskew capability for phase alignment. The receiver maintains a constant energy-per-bit consumption across 16-32 Gb/s by adaptive body biasing in a 28 nm FDSOI technology.

Design considerations for high-density fully intraocular epiretinal prostheses

Retinal prostheses have successfully proven to be a viable treatment for advanced stages of retinal degenerative diseases such as retinitis pigmetosa. However, current implementations have critical limitations that affect their functionality and resolution. This paper reviews design challenges of the electronics considering the biology of the eye and discusses new approaches for future high-density fully intraocular prostheses. An origami retinal implant that has the potential to alleviate the size, power and cost constraints of such systems is proposed. Measured results of enabling technologies are also discussed.

A 10Gb/s, 342fJ/bit micro-ring modulator transmitter with switched-capacitor pre-emphasis and monolithic temperature sensor in 65nm CMOS

In this work, a CMOS-SiPh optical transmitter based on carrier-injection ring modulators is presented. It features a novel low-power switched-capacitor-based pre-emphasis that effectively compensates the modulator bandwidth limitation. A wavelength stabilization technique via direct measurement of ring temperature using a monolithic PTAT sensor is also presented. The optical transmitter achieves energy efficiency of 342fJ/bit at 10Gb/s and the wavelength stabilization circuit consumes 0.29mW.

A 20Gb/s 0.77pJ/b VCSEL transmitter with nonlinear equalization in 32nm SOI CMOS

This paper describes an ultra-low-power VCSEL transmitter in 32nm SOI CMOS. To increase its power efficiency, the VCSEL is driven at a low bias current. The resulting nonlinearity and loss in bandwidth is modelled and compensated by a nonlinear equalization technique. The time domain optical responses for “one” and “zero” bits are used to find the optimum equalization technique. The rising and falling edges were equalized separately and the equalization delay is selected based on the bias current of the VCSEL. The transmitter achieves energy efficiency of 0.77pJ/b at 20Gb/s.