Azita Emami-Neyestanak

A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects

An optical interconnect transceiver incorporates a 4-tap FIR TX to reduce VCSEL average current and an integrating/double-sampling RX to eliminate the need for a bit-rate TIA. A dual-loop CDR with baud-rate phase detection further reduces power and area. Fabricated in a 1V 90nm CMOS process, the transceiver achieves 16Gb/s operation while consuming 129mW and occupying 0.105mm2

A Nonuniform Sampler for Wideband Spectrally-Sparse Environments

We present a wide bandwidth, compressed sensing based nonuniform sampling (NUS) system with a custom sample-and-hold chip designed to take advantage of a low average sampling rate. By sampling signals nonuniformly, the average sample rate can be more than a magnitude lower than the Nyquist rate, provided that these signals have a relatively low information content as measured by the sparsity of their spectrum. The hardware design combines a wideband Indium-Phosphide heterojunction bipolar transistor sample-and-hold with a commercial off-the-shelf analog-to-digital converter to digitize an 800 MHz to 2 GHz band (having 100 MHz of noncontiguous spectral content) at an average sample rate of 236 Ms/s. Signal reconstruction is performed via a nonlinear compressed sensing algorithm, and the challenges of developing an efficient implementation are discussed. The NUS system is a general purpose digital receiver. As an example of its real signal capabilities, measured bit-error-rate data for a GSM channel is presented, and comparisons to a conventional wideband 4.4 Gs/s ADC are made.

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally

A Compressed Sensing Parameter Extraction Platform for Radar Pulse Signal Acquisition

In this paper we present a complete (hardware/ software) sub-Nyquist rate (× 13) wideband signal acquisition chain capable of acquiring radar pulse parameters in an instantaneous bandwidth spanning 100 MHz-2.5 GHz with the equivalent of 8 effective number of bits (ENOB) digitizing performance. The approach is based on the alternative sensing-paradigm of compressed sensing (CS). The hardware platform features a fully-integrated CS receiver architecture named the random-modulation preintegrator (RMPI) fabricated in Northrop Grummans 450 nm InP HBT bipolar technology. The software back-end consists of a novel CS parameter recovery algorithm which extracts information about the signal without performing full time-domain signal reconstruction. This approach significantly reduces the computational overhead involved in retrieving desired information which demonstrates an avenue toward employing CS techniques in power-constrained real-time applications. The developed techniques are validated on CS samples physically measured by the fabricated RMPI and measurement results are presented. The parameter estimation algorithms are described in detail and a complete description of the physical hardware is given.

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm2.

Design and implementation of a fully integrated compressed-sensing signal acquisition system

Compressed sensing (CS) is a topic of tremendous interest because it provides theoretical guarantees and computationally tractable algorithms to fully recover signals sampled at a rate close to its information content. This paper presents the design of the first physically realized fully-integrated CS based Analog-to-Information (A2I) pre-processor known as the Random-Modulation Pre-Integrator (RMPI) [1]. The RMPI achieves 2GHz bandwidth while digitizing samples at a rate 12.5× lower than the Nyquist rate. The success of this implementation is due to a coherent theory/algorithm/hardware co-design approach. This paper addresses key aspects of the design, presents simulation and hardware measurements, and discusses limiting factors in performance.

A 24-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication

This paper describes a dense, high-speed, and low-power CMOS optical receiver implemented in a 65-nm CMOS technology. High data rate is achieved using an RC double-sampling front-end and a novel dynamic offset-modulation technique. The low-voltage double-sampling technique provides high power efficiency by avoiding linear high-gain elements conventionally employed in transimpedance-amplifier (TIA) receivers. In addition, the demultiplexed output of the receiver helps save power in the following digital blocks. The receiver functionality was validated by electrical and optical measurements. The receiver achieves up to 24 Gb/s data rate with better than 160-μA current sensitivity in an experiment performed by a photodiode current emulator embedded on-chip. Optical measurements performed by a 1550-nm wire-bonded photodiode show better than - 4.7-dBm optical sensitivity at 24 Gb/s. The receiver offers peak power efficiency of 0.36 pJ/b at 20 Gb/s from a 1.2-V supply and occupies less than 0.0028 mm2 silicon area.

A 100MHz–2GHz 12.5x sub-Nyquist rate receiver in 90nm CMOS

A fully-integrated, high-speed, wideband receiver called the random modulation pre-integrator is realized in IBM 90nm digital CMOS. It achieves an effective instantaneous bandwidth of 2GHz, with >;54dB dynamic range. Most notably, the aggregate digitization rate is fs =320MSPS, 12.5× below the Nyquist rate. Signal recovery can be accomplished for any signal with a concise representation. The system is validated using radar-pulses and tones as the input and recovering the time-domain waveforms.

A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation

The increasing demand for high-bandwidth interconnection between integrated circuits requires large numbers of I/Os per chip as well as high data rates per I/O. Key limitations in meeting these requirements include channel characteristics and I/O power consumption. Even in short interconnects, the channel attenuation at very high data rates is significant, and using receiver equalization can greatly improve the link performance [1–5]. However, compensating a high level of loss requires many taps of equalization, which can significantly reduce the power efficiency of the link. Parallel data transmission increases the aggregate data rate, but compact traces placed in close proximity suffer from a high level of crosstalk interference. This problem is exacerbated when transmit pre-emphasis techniques are exploited to boost the high frequency gain. While the use of differential signaling can mitigate the effect of crosstalk, it requires twisting pairs leading to area and bandwidth penalties.

CMOS transceiver with baud rate clock recovery for optical interconnects

An efficient baud rate clock and data recovery architecture is applied to a double sampling/integrating front-end receiver for optical interconnects. Receiver performance is analyzed and projected for future technologies. This front-end allows use of a 1:5 demux architecture to achieve 5Gb/s in a 0.25 /spl mu/m CMOS process. A 5:1 multiplexing transmitter is used to drive VCSELs for optical transmission. The transceiver chip consumes 145mW per link at 5Gb/s with a 2.5V supply.