Meisam Honarvar Nazari

CMOS Neurotransmitter Microarray: 96-Channel Integrated Potentiostat With On-Die Microsensors

A 8 × 12 array of integrated potentiostats for on-CMOS neurotransmitter imaging is presented. Each potentiostat channel measures bidirectional redox currents proportional to the concentration of a neurochemical. By combining the current-to-frequency and the single-slope analog-to-digital converter (ADC) architectures a total linear dynamic range of 95 dB is achieved. A 3.8 mm × 3.1 mm prototype fabricated in a 0.35 μm standard CMOS technology was integrated with flat and 3D on-die gold microelectrodes and an on-chip microfluidic network. It is experimentally validated in in-situ recording of neurotransmitter dopamine.

A 24-Gb/s Double-Sampling Receiver for Ultra-Low-Power Optical Communication

This paper describes a dense, high-speed, and low-power CMOS optical receiver implemented in a 65-nm CMOS technology. High data rate is achieved using an RC double-sampling front-end and a novel dynamic offset-modulation technique. The low-voltage double-sampling technique provides high power efficiency by avoiding linear high-gain elements conventionally employed in transimpedance-amplifier (TIA) receivers. In addition, the demultiplexed output of the receiver helps save power in the following digital blocks. The receiver functionality was validated by electrical and optical measurements. The receiver achieves up to 24 Gb/s data rate with better than 160-μA current sensitivity in an experiment performed by a photodiode current emulator embedded on-chip. Optical measurements performed by a 1550-nm wire-bonded photodiode show better than - 4.7-dBm optical sensitivity at 24 Gb/s. The receiver offers peak power efficiency of 0.36 pJ/b at 20 Gb/s from a 1.2-V supply and occupies less than 0.0028 mm2 silicon area.

A 15-Gb/s 0.5-mW/Gbps Two-Tap DFE Receiver With Far-End Crosstalk Cancellation

The increasing demand for high-bandwidth interconnection between integrated circuits requires large numbers of I/Os per chip as well as high data rates per I/O. Key limitations in meeting these requirements include channel characteristics and I/O power consumption. Even in short interconnects, the channel attenuation at very high data rates is significant, and using receiver equalization can greatly improve the link performance [1–5]. However, compensating a high level of loss requires many taps of equalization, which can significantly reduce the power efficiency of the link. Parallel data transmission increases the aggregate data rate, but compact traces placed in close proximity suffer from a high level of crosstalk interference. This problem is exacerbated when transmit pre-emphasis techniques are exploited to boost the high frequency gain. While the use of differential signaling can mitigate the effect of crosstalk, it requires twisting pairs leading to area and bandwidth penalties.

A Fully Intraocular High-Density Self-Calibrating Epiretinal Prosthesis

This paper presents a fully intraocular self-calibrating epiretinal prosthesis with 512 independent channels in 65 nm CMOS. A novel digital calibration technique matches the biphasic currents of each channel independently while the calibration circuitry is shared among every 4 channels. Dual-band telemetry for power and data with on-chip rectifier and clock recovery reduces the number of off-chip components. The rectifier utilizes unidirectional switches to prevent reverse conduction loss in the power transistors and achieves an efficiency > 80%. The data telemetry implements a phase-shift keying (PSK) modulation scheme and supports data rates up to 20 Mb/s. The system occupies an area of 4.5 ×3.1 mm2. It features a pixel size of 0.0169 mm2 and arbitrary waveform generation per channel. In vitro measurements performed on a Pt/Ir concentric bipolar electrode in phosphate buffered saline (PBS) are presented. A statistical measurement over 40 channels from 5 different chips shows a current mismatch with μ = 1.12 μA and σ = 0.53 μA. The chip is integrated with flexible MEMS origami coils and parylene substrate to provide a fully intraocular implant.

A fully differential CMOS potentiostat

A CMOS potentiostat for chemical sensing in a noisy environment is presented. The potentiostat measures bidirectional electrochemical redox currents proportional to the concentration of a chemical down to pico-ampere range. The fully differential architecture with differential recording electrodes suppresses the common mode interference. A 200µm×200µm prototype was fabricated in a standard 0.35µm standard CMOS technology and yields a 70dB dynamic range. The in-channel analog-to-digital converter (ADC) performs 16-bit current-to-frequency quantization. The integrated potentiostat functionality is validated in electrical and electrochemical experiments.

An implantable continuous glucose monitoring microsystem in 0.18µm CMOS

We present a fully implantable subcutaneous continuous glucose monitoring (CGM) microsystem on CMOS platform. The proposed design incorporates electrochemical sensing technique using an ultra-low-power potentiostatic system. It is wirelessly powered through an inductive coupling link at 900MHz and supports bidirectional data communication with an external reader. A low-power potentiostat and a dual-slope ADC record the on-chip sensor signal. Pt and Ag/AgCl on-chip electrodes are post-fabricated and functionalized in situ by glucose oxidase enzyme to enable glucose measurement. The 1.4×1.4×0.25mm3 prototype fabricated in a 0.18μm CMOS technology was validated in glucose measurements. Total power consumption of the system is 6μW.

192-channel CMOS neurochemical microarray

A 16×12-channel neurochemical microarray is presented. Each channel acquires bidirectional currents down to pico-amperes proportional to the concentration of a neurochemical. By combining the current-to-frequency and the single-slope analog-to-digital converter (ADC) 110dB of dynamic range is achieved. The ADC in each channel generates a 16-bit output in less than a millisecond. The microarray with flat and 3D gold electrodes and an on-chip microfluidic network is experimentally validated in in-situ recording of neurotransmitter dopamine.

An 18.6Gb/s double-sampling receiver in 65nm CMOS for ultra-low-power optical communication

Using optics for chip-to-chip interconnects has recently gained a lot of interest. As data rates scale to meet increasing bandwidth requirements, the shortcomings of copper channels are becoming more severe. Hybrid integration of optical devices with electronics has been demonstrated to achieve high performance, and recent advances in silicon photonics have led to fully integrated optical signaling. These approaches pave the way to massively parallel optical communications. Dense arrays of optical detectors require very low-power, sensitive, and compact optical receiver circuits. Existing designs for the input receiver, such as TIA, require large power consumption to achieve high band width and low noise, and can occupy large area due to bandwidth-enhancement inductors. In this work, a compact low-power optical receiver that scales well with technology is designed to explore the potential of optical signaling for future chip-to-chip and on-chip communication.

A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS

A new 1-tap predictive decision feedback equalizer (prDFE), implemented in 40-nm CMOS LP process, achieves 27-Gb/s operation with 0.41-mW/Gb/s power efficiency. The prDFE employs a novel quad-data rate sampling architecture to improve power efficiency while minimizing critical feedback path timing constraint of the equalizer to enable post-cursor inter-symbol interference (ISI) cancellation at high data-rate operations.

Ultra low-power receiver design for dense optical interconnects

In this work, a compact low-power optical receiver that scales well with technology has been designed to explore the potential of optical signaling for future chip-to-chip and on-chip communication. The proposed receiver resolves the problem by employing an integrating RC front-end along with dynamic offset modulation technique that decouple the bandwidth/data-rate and integration/headroom trade-offs.