Azlina Mohd Zain

Study on pH sensing properties of RF magnetron sputtered tantalum pentoxide (Ta 2 O 5 ) thin film

The pH-sensing properties of tantalum pentoxide (Ta2O5) film deposited by RF magnetron reactive sputtering method is demonstrated. The tantalum pentoxide film on silicon wafer samples were characterized by capacitance-voltage (C-V) measurements. The samples were annealed in ambient condition at 400°C for several hours. High frequency C-V measurements were performed on the wafer samples at pH levels of 4, 7 and 10. Results obtained from the C-V measurements showed good linearity in the selected pH range. The pH sensitivity has reached 62mV/pH, which is better than the theoretical Nernst potential.

The elimination of poly stringer in double poly AMS technology development

Defects found during the fabrication of poly-insulator-poly (PIP) analog mixed signal (AMS) device using 0.35mum CMOS technology process had revealed the existence of poly stringers. The formation of stringer is due to topography of the double poly PIP capacitor structure. The challenge in eliminating the stringer is to develop an optimal polysilicon gate etch process that can remove the stringer completely as well as maintaining a good polysilicon gate profile at logic CMOS area. Three types of approaches have been experimented to solve the stringer issue. It is proven that combining a thinner bottom plate (poly1) film together with an optimized polysilicon gate etching condition had been successful in eliminating the stringer completely

Self-aligned nanostructures by CMOS technology

In semiconductor fabrication, there are various methods that can be employed to form fine structures. Such techniques include a combination of advance lithography and etching, chemical mechanical planarization (CMP), or metal lift-off. However, these techniques may not be the easiest or the most cost effective. When using lithographic methods such as ultraviolet (UV), deep ultraviolet (DUV), extended ultraviolet (EUV), E-Beam [1], and X-ray, there are always resolution and alignment issues such as how small a structure can be produced and how closely and accurately a structure can be aligned to another. Even when lithography issues are resolved, patterning of very fine structures is also a problem. Wet chemical etching is not feasible when trying to produce submicrometer features because of large undercuts due to the isotropic nature of the etch solution. Lift-off with sacrificial resist [2] is a more common solution to produce nanostructures, but the technique does have resist imposed limitations where deposition must take place below 200°C because of resist thermal stability preventing its use with chemical vapour deposition processes. Also, organizing nanostructures into highly ordered array can also prove extremely challenging.

Characterization of Contact Etching Profile for 0.35um Analog Mixed Signal Product Development

An Analog Mixed Signal (AMS) device incorporating polysilicon insulator polysilicon (PIP) capacitor and polyresistor sub-modules has been fabricated using 0.35um CMOS technology. Addition of the analog sub-modules has introduced topography height difference between the PIP capacitor region and the MOS transistor region. The resultant topography had resulted in variation of the pre-metal dielectric (PMD) layer thickness where contact holes will be formed. Topography height difference had also resulted in PMD layer thickness variation between one location to another. The thickest PMD layer was located on the MOS transistor active region, while the thinnest PMD layer was on the polyresistor region. Etching contact holes on such topography along with different etch stop materials is challenging. Hence, contact etching process needs to be optimized to ensure contact holes at all locations are cleared without too much overetching of the underlying layer. Furthermore, the etched profile needs to be slightly tapered to achieve good barrier metal step coverage. A new contact etching process that fulfilled the device requirements with good contact resistance parameters has been developed. The process optimization experiments and the electrical test results of the contact resistance are presented and discussed in this paper.