Mohd Rofei Mat Hussin

TCAD process simulation for light effect improvement of ion sensitive field effect transistor

The conventional open gate ISFET sensor is normally very sensitive to light exposure which influences the sensor characteristics. In this study, different process conditions of ISFET were simulated using SILVACO TCAD in order to find the right doping profile which minimizes light effect. Various channels doping levels for ISFET sensor have been analyzed. Comparison with SRP samples was done in order to ensure the accuracy of the simulation output. Based on simulation results, the ISFETs were then fabricated and tested under the same intensities of light exposure and ambient temperatures. It shows that ISFET which underwent double PWELL implant and with deeper junction depth experiences lower light effect. This paper will discuss on how doping profiles affect ISFET performance with respect to light effect.

Simulation and Fabrication of Extended Gate Ion Sensitive Field Effect Transistor for Biosensor Application

A biosensor is an analytical device, used for the detection of an analyte, that combines a biological component with a physicochemical detector.

Design and Fabrication of Low Voltage Silicon Trench MOS Barrier Schottky Rectifier for High Temperature Applications

This paper presents the design, fabrication, and characterization of 60V and 100V silicon Trench MOS Barrier Schottky (TMBS) rectifier. The devices were designed for switching power supplies operated in high temperature environment. Design considerations of silicon TMBS rectifiers are discussed in this paper. Trench structure design and trench oxide were improved to produce low reverse leakage current and high device performance. As a result, TMBS rectifiers with blocking voltage of up to 60V and 100V were successfully fabricated. The tradeoff between reverse leakage current and forward voltage drop are well controlled at high operating temperature (>75°C).

Preparation of conductive cellulose paper through electrochemical exfoliation of graphite: The role of anionic surfactant ionic liquids as exfoliating and stabilizing agents

A facile electrochemical exfoliation method was established to efficiently prepare conductive paper containing reduced graphene oxide (RGO) with the help of single chain anionic surfactant ionic liquids (SAILs). The surfactant ionic liquids are synthesized from conventional organic surfactant anions and a 1-butyl-3-methyl-imidazolium cation. For the first time the combination of SAILs and cellulose was used to directly exfoliate graphite. The ionic liquid 1-butyl-3-methyl-imidazolium dodecylbenzenesulfonate (BMIM-DBS) was shown to have notable affinity for graphene, demonstrating improved electrical properties of the conductive cellulose paper. The presence of BMIM-DBS in the system promotes five orders of magnitude enhancement of the paper electrical conductivity (2.71 × 10-5 S cm-1) compared to the native cellulose (1.97 × 10-10 S cm-1). A thorough investigation using electron microscopy and Raman spectroscopy highlights the presence of uniform graphene incorporated inside the matrices. Studies into aqueous aggregation behavior using small-angle neutron scattering (SANS) point to the ability of this compound to act as a bridge between graphene and cellulose, and is responsible for the enhanced exfoliation level and stabilization of the resulting dispersion. The simple and feasible process for producing conductive paper described here is attractive for the possibility of scaling-up this technique for mass production of conductive composites containing graphene or other layered materials.

Effect of source-drain metal shield in FET structure on drain leakage current

This study presents the effect of source-drain metal shield in FET structure on drain leakage current. The FET structure was fabricated on the wafer by using MIMOSs standard fabrication process. Aluminum (Al) was sputtered with thickness of 400 nm as metal shield layer at the source and drain area of FET structure. There are four different layout designs of source-drain metal shield that were tested by Keithley 236 current-voltage sourcing under light and dark conditions. The measurements were carried out in a dark box with controllable light intensity. Besides the drain leakage current investigation, this study also investigates the light effect of various layout designs with source-drain metal shield on FET structure. It was found that the layout design with source-drain metal shield has lower drain leakage current compared to the layout design without source-drain metal shield. However, the various layout design of source-drain metal shield cannot eliminate the light effect.

Fault isolation with backside polish for trench Schottky diode

Photon Emission Microscopy (PEM) is one of the well-known fault isolation tool used in most failure analysis lab. The tool works on a principle whereby light will be emitted from the electron-hole pair recombination and carrier excitation when there is junction breakdown. However, this light emission is very weak causing fault isolation impossible to be detected on front side of Schottky diode wafer which is covered with thick Aluminium metallization. Therefore, a backside polishing method is required to thin the bulk Silicon to allow optimum transmission and thus failure site localization. In this study, Schottky diode wafer which has failed low (early) junction breakdown was thin down from total thickness of 640um. Final thickness of 40um does reveal an emission but do not able to show the die pattern. Emission was detected using InGaAs camera (λ=900nm to 1600nm). Die pattern is needed to be seen from the backside to be able to locate the exact fault localization spot on the front side. Die were further thin down to final thickness of 30um of total thickness including metallization. This paper will reveal the steps taken to polish die backside which is done by using ASAP-1 Ultratec sample preparation tool. Results showed that after thinning bulk Silicon to 30um with mirror finishing, die pattern was clearly visible. Fault localization done using PHEMOS 1000 where emission spot observed and samples were continued with cross-sectioning analysis. Cross-sectional analysis using Dual Beam system showed that there is Aluminium metallization diffused into mesa and trench region. Aluminium migration into these regions will cause high leakage and lowe (early) junction breakdown failure on the trench Schottky diode.