B. H. Lee

Analog memory and spike-timing-dependent plasticity characteristics of a nanoscale titanium oxide bilayer resistive switching device.

We demonstrated analog memory, synaptic plasticity, and a spike-timing-dependent plasticity (STDP) function with a nanoscale titanium oxide bilayer resistive switching device with a simple fabrication process and good yield uniformity. We confirmed the multilevel conductance and analog memory characteristics as well as the uniformity and separated states for the accuracy of conductance change. Finally, STDP and a biological triple model were analyzed to demonstrate the potential of titanium oxide bilayer resistive switching device as synapses in neuromorphic devices. By developing a simple resistive switching device that can emulate a synaptic function, the unique characteristics of synapses in the brain, e.g. combined memory and computing in one synapse and adaptation to the outside environment, were successfully demonstrated in a solid state device.

Variability and feasibility of CVD graphene interconnect

Graphene and its derivatives (graphite, CNT) have very high conductivity and critical current density higher than 108 A/cm2, which can be utilized in interconnect applications. Theoretically, a doped graphene is predicted to have better performance than Cu as an interconnect conductor. However, the feasibility of graphene interconnect has not been experimentally examined systematically. In this paper, the critical current density of single layer and multilayer graphene are studied to provide insights about the feasibility of graphene interconnect technology.

Effects of high pressure hydrogen and deuterium annealing on nMOSFET with Hf-base gate dielectrics

Introduction Mobility degradation of high-k MOSFET is one of the major concern for aggressively scaled CMOSFET technologies. In general, carrier mobility of n-channel high-k MOSFET is more severely degraded than that of p-channel device.[1] It can be explained by high interface trap density in the upper half of the band-gap, which preferential affects n-channel MOSFET.[2] It is well known that forming gas anneal at 400-450C is sufficient to completely passivate the interface state of SiO2 gate dielectric. However, conventional forming gas annealing at 400-450C is not sufficient for high-k gate dielectric.[3-4] Recently we reported improved interface characteristics of HfO2 MIS capacitors by employing high pressure anneal.[5] In this paper, we have investigated, the effect of high pressure pure (100%) hydrogen annealing on electrical and reliability characteristics of high-k nMOSFET.

Mechanisms of ambient dependent mobility degradation in the graphene MOSFETs on SiO 2 substrate

Two different mechanisms affecting the device instability and mobility degradation at graphene MOSFET on SiO2 substrate and their time constant, 40μsec and ~ 370μsec, have been identified. Oxygen/H2O reaction at the surface of graphene was identified as a major source of device hysteresis causing mobility degradation and device instability.