B. Hochet

New encoding scheme for high-speed flash ADC's

A new encoding scheme for high-speed flash analog to digital converters using a Wallace tree is described. It provides a global error filtering and its regular topology optimises the signal propagation. Its application to a 5-bit 1.4-GHz Gallium Arsenide analog-to-digital converter is described.

Implementation of a learning Kohonen neuron based on a new multilevel storage technique

A compact implementation of a fully parallel Kohonen network with learning capabilities is described. Implementation issues concerning general neural networks are briefly explored, and an original mixed analog and digital technique for storing discrete voltages on a capacitor is presented. The limitations are discussed, and measurements on the storage dynamics are reported, showing that 8 b of resolution can be achieved. This technique is applied to the realization of a neuron dedicated to Kohonen maps. This neuron has been implemented in a standard 2- mu m CMOS technology, and the synaptic functions are very dense. The implementation uses a standard 8-b integer arithmetic. Efficient and consistent encoding of the information, dynamic storage, and the adaptation of the synaptic weights and the synaptic multipliers use simple circuitry, thus leading to a low number of transistors. >

Quantization effects in digitally behaving circuit implementations of Kohonen networks

Implementing a neural network on a digital or mixed analog and digital chip yields the quantization of the synaptic weights dynamics. This paper addresses this topic in the case of Kohonens self-organizing maps. We first study qualitatively how the quantization affects the convergence and the properties, and deduce from this analysis the way to choose the parameters of the network (adaptation gain and neighborhood). We show that a spatially decreasing neighborhood function is far more preferable than the usually rectangular neighborhood function, because of the weight quantization. Based on these results, an analog nonlinear network, integrated in a standard CMOS technology, and implementing this spatially decreasing neighborhood function is then presented. It can be used in a mixed analog and digital circuit implementation.

Pseudo-complementary FET logic (PCFL): a low-power logic family in GaAs

This paper describes an efficient low-power static logic family in GaAs, called PCFL for pseudo-complementary FET logic. Its behavior mimics that of CMOS by compensating the lack of complementary transistors with the use of complementary logic signals. Like any nonratioed logic, PCFL allows the realization of complex gates. It is fully compatible with DCFL and two-phase dynamic FET Logic (TDFL). Using enhancement-mode FETs only, PCFL benefits from good process variations immunity and good noise margins. Measurement results on a ring oscillator, an inverter chain, and a frequency divider are reported. PCFL is shown to operate at 500 MHz with a 0.6 /spl mu/m MESFET process. The power consumption of an inverter is about 10 /spl mu/W at 100 MHz.

Implementation of a fully parallel Kohonen map: a mixed analog digital approach

This paper describes the CMOS implementation of a digitally behaving Kohonen map. Although input values and synaptic weights are quantized, the basic blocks are implemented using digital or analog techniques where best suited, combined with efficient information encoding. This has lead the authors to the design of a modular 4/spl times/4 Kohonen neuron chip that may be cascaded in order to realize large size fully parallel Kohonen maps.<<ETX>>

Implementation of a Kohonen map with learning capabilities

An efficient and compact implementation of Kohonen neural networks with learning capability is described. Each synaptic weight is stored as a discrete voltage on a capacitor. The neurons compute the Manhattan distance between the input vector and their own synaptic vector using a dedicated arithmetics. The neighborhoods used during the learning phase are computed using a nonlinear resistor-based network.<<ETX>>

A divided decoder-matrix (DDM) structure and its application to a 8 kb GaAs MESFET ROM

This paper describes a new approach which allows the realization of both low-power and high storage capacity ROMs in GaAs. In this technique, called DDM (Divided Decoder Matrix), low-power operation is obtained by powering down the parts which are not situated in the addressing path, while high-storage capability is obtained by limiting the leakage currents in the ROM matrix. As an application of the DDM technique, an 8 Kbit MESFET ROM has been designed with a standard 0.6 /spl mu/m-gate MESFET process. The ROM has a typical access time of 1.2 ns and a power dissipation of 60 mW.

A low-power GaAs MESFET dual-modulus prescaler

A structure for a high speed low-power GaAs dual-modulus frequency divider is presented in this paper. By using a new flip-flop, simulations predict a lower power consumption than previously reported CMOS and GaAs circuits. The prescaler has been fabricated with a standard 0.6 /spl mu/m MESFET technology verifying the expected low power dissipation.

Performance/power tradeoffs in high-speed GaAs ADCs

While designing very high-speed analog-to-digital converters, the power consumption is usually neglected in the search for performance. However, it should be taken into account, for commercial reasons as well as for technical ones (cooling issues). The converter architecture is of a critical importance for optimizing the performance/power tradeoff of a converter. The aim of this paper is to decide, for a given technology, in this case a GaAs MESFET technology, which architecture exhibits the best trade-off between power consumption and performances.

Field Effect Transistor Memory Circuits

The sections in this article are 1 Direct-Coupled Field-Effect Transistor Logic 2 Field Effect Memory Problems Analysis 3 Proposed Solutions to Minimize Leakage Current 4 Proposed Solutions to Improve Yield 5 Proposed Solution to Improve the Soft-Error Immunity 6 Proposed Solutions to Minimize the Power Dissipation 7 Proposed Solution to Increase the Speed 8 Commercial Static Srams 9 Commercial Roms 10 Design of Silicon Rams Using Complementary Gallium Arsenide